公开(公告)号：US20230139574A1

公开(公告)日：2023-05-04

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGUN YOU ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US10153358B2

公开(公告)日：2018-12-11

申请号：US15390754

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungseok Min ,  Seongjin Nam ,  Sughyun Sung ,  Youngmook Oh ,  Migyeong Gwon ,  Hyungdong Kim ,  InWon Park ,  Hyunggoo Lee

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/683

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

公开(公告)号：US12237391B2

公开(公告)日：2025-02-25

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US12034060B2

公开(公告)日：2024-07-09

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US11362196B2

公开(公告)日：2022-06-14

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L21/8234

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US10332779B2

公开(公告)日：2019-06-25

申请号：US15342456

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok Min ,  Moojin Kim ,  Seongjin Nam ,  Sughyun Sung ,  YoungHoon Song ,  Youngmook Oh

IPC: H01L21/02 ,  H01L21/762 ,  H01L27/108 ,  H01L21/3065 ,  H01L21/311

Abstract: A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.