公开(公告)号：US11815997B2

公开(公告)日：2023-11-14

申请号：US17814964

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

IPC: H03M13/00 ,  G06F11/10 ,  G06F11/07 ,  G06F17/16 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F17/16 ,  H03M13/1575

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

公开(公告)号：US20230147227A1

公开(公告)日：2023-05-11

申请号：US17814964

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhun Lim ,  Kijun Lee ,  Myungkyu Lee ,  Eunchul Kwon ,  Hoyoun Kim ,  Jongmin Lee

IPC: G06F11/10 ,  G06F11/07 ,  H03M13/15 ,  G06F17/16

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/076 ,  H03M13/1575 ,  G06F17/16

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

公开(公告)号：US11437115B2

公开(公告)日：2022-09-06

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Hoyoun Kim ,  Suhun Lim ,  Sunghye Cho

IPC: G11C29/00 ,  G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.