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    NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    2.
    发明公开
    NONVOLATILE MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240079280A1

    公开(公告)日：2024-03-07

    申请号：US18322714

    申请日：2023-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Do Hyung Kim ,  Ji Young Kim ,  Ji Won Kim ,  Suk Kang Sung ,  Woo Sung Yang

    IPC: H01L21/66

    CPC classification number: H01L22/34

    Abstract: There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

    SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20230403854A1

    公开(公告)日：2023-12-14

    申请号：US18180437

    申请日：2023-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Young Kim ,  Do Hyung Kim ,  Ji Won Kim ,  Suk Kang Sung

    IPC: H10B43/27 ,  H10B80/00

    CPC classification number: H10B43/27 ,  H10B80/00

    Abstract: According to some implementations of the present disclosure, a semiconductor memory device includes a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including: a plate disposed on the second face of the semiconductor layer; and a plug extending from the plate through the semiconductor layer; a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one an other; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11956957B2

    公开(公告)日：2024-04-09

    申请号：US17203122

    申请日：2021-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji Young Kim ,  Woo Sung Yang ,  Sung-Min Hwang ,  Suk Kang Sung ,  Joon-Sung Lim

    IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

    Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

    Semiconductor memory device and electronic system including the same
    9.
    发明授权
    Semiconductor memory device and electronic system including the same 有权

    公开(公告)号：US11844211B2

    公开(公告)日：2023-12-12

    申请号：US17340148

    申请日：2021-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

    IPC: H10B41/27 ,  H01L23/538 ,  H01L25/065 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L23/5384 ,  H01L25/0657 ,  H10B43/27

    Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

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