公开(公告)号：US12094846B2

公开(公告)日：2024-09-17

申请号：US18349017

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/535 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US20240179910A1

公开(公告)日：2024-05-30

申请号：US18355718

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyoung Kim ,  Ji Won Kim ,  Ah Reum Lee ,  Suk Kang Sung

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device includes a cell substrate including a first surface and a second surface opposite to the first surface, a first mold stack including a plurality of first gate electrodes sequentially stacked on the first surface, a second mold stack including a plurality of second gate electrodes sequentially stacked on the first mold stack, a first channel structure extending in a first direction with respect to the first surface and crossing the plurality of first gate electrodes and the plurality of second gate electrodes, and an input/output pad on the second surface, wherein the first mold stack includes a mold opening that exposes a portion of the second mold stack, and at least a portion of the input/output pad overlaps the mold opening in the first direction.

公开(公告)号：US11061478B2

公开(公告)日：2021-07-13

申请号：US16835462

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Gu Lee ,  Ji Won Kim ,  Young Hak Oh ,  Sun Young Yi ,  Won Jun Lee ,  Kyu Ok Choi

IPC: G08B6/00 ,  G06F3/01 ,  G06F1/16 ,  G06F3/0488 ,  H04M1/72412

Abstract: An electronic device includes a communication circuit to communicate with at least one wearable device, and at least one processor electrically connected with the communication circuit. The at least one processor is configured to obtain position information on a position on which the at least one wearable device is placed on a user's body, and to transmit a control signal to the at least one wearable device through the communication circuit such that, when an output of a haptic pattern specified based on a function is requested, the at least one wearable device outputs a haptic feedback corresponding to the position information and the specified haptic pattern.

公开(公告)号：US09616424B2

公开(公告)日：2017-04-11

申请号：US13730554

申请日：2012-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Seok Lee ,  Ji Won Kim ,  Jeong Gun Lee ,  Kui Hyun Kim

IPC: B01L3/00 ,  G01N21/07 ,  G01N33/543 ,  G01N35/00

CPC classification number: B01L3/50273 ,  B01L3/502738 ,  B01L3/545 ,  B01L2200/0621 ,  B01L2200/0689 ,  B01L2200/10 ,  B01L2300/021 ,  B01L2300/0806 ,  B01L2300/0816 ,  B01L2300/0861 ,  B01L2300/161 ,  B01L2300/1827 ,  B01L2400/0406 ,  B01L2400/0409 ,  B01L2400/0677 ,  G01N21/07 ,  G01N33/54386 ,  G01N35/00069

Abstract: Provided is a microfluidic apparatus including: a microfluidic structure for providing spaces for receiving a fluid and for forming channels, through which the fluid flows; and valves for controlling the flow of fluid through the channels in the microfluidic apparatus. The microfluidic structure includes: a sample chamber; a sample separation unit receiving the sample from the sample chamber and separating a supernatant from the sample by using a centrifugal force; a testing unit receiving the supernatant from the sample separation unit for detecting a specimen from the supernatant using an antigen-antibody reaction, and a quality control chamber for identifying reliability of the test.

公开(公告)号：US11715712B2

公开(公告)日：2023-08-01

申请号：US17323076

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Ji Won Kim ,  Jae Ho Ahn ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L23/562 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

公开(公告)号：US10261615B2

公开(公告)日：2019-04-16

申请号：US15584305

申请日：2017-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Young Lee ,  Gyu Chual Kim ,  Bo Keun Kim ,  Ji Won Kim ,  Kyu Ok Choi

IPC: G06F3/041 ,  G06F3/0488

Abstract: An electronic device includes a touch sensitive display, and a processor electrically connected with the touch sensitive display. The processor is configured to sense a first touch and a second touch on the touch sensitive display, to display a first region expanding with respect to a location at which the first touch is made, on the touch sensitive display, to display a second region expanding with respect to a location at which the second touch is made, on the touch sensitive display, and to display a specified screen in the touch sensitive display if a sum of an area of the first region and an area of the second region exceeds a specified value.

公开(公告)号：US20140177943A1

公开(公告)日：2014-06-26

申请号：US14017962

申请日：2013-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang Ho Cho ,  Ho Young Lee ,  Ji Won Kim

IPC: G06T19/20

CPC classification number: G06T19/20 ,  H04N13/111

Abstract: A method and apparatus for generating a multi-view image, the method including determining an input image for generating multi-view images, and selecting a total of stereo images or one of stereo images to be the input image based on a presence of a distortion between the stereo images.

Abstract translation: 一种用于产生多视点图像的方法和装置，所述方法包括：确定用于生成多视图图像的输入图像，以及基于失真的存在，选择立体图像或立体图像之一作为输入图像的总和 在立体图像之间。

公开(公告)号：US11844211B2

公开(公告)日：2023-12-12

申请号：US17340148

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H10B41/27 ,  H01L23/538 ,  H01L25/065 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5384 ,  H01L25/0657 ,  H10B43/27

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

公开(公告)号：US11728304B2

公开(公告)日：2023-08-15

申请号：US17240641

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho Ahn ,  Ji Won Kim ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/535 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US11715713B2

公开(公告)日：2023-08-01

申请号：US17405637

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Won Kim ,  Jae Ho Ahn ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Suk Kang Sung

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.