Apparatus and method for ZQ calibration

    公开(公告)号:US12237043B2

    公开(公告)日:2025-02-25

    申请号:US17984757

    申请日:2022-11-10

    Abstract: There are provided an apparatus and method for performing impedance control (ZQ) calibration without a ZQ pin and an external resistor. The apparatus includes an output driver circuit connected to a signal pin interfacing with an external device; a register control word (RCW) configured to store an output driver impedance parameter related to a pull-up output voltage (VOH) condition of the signal pin; and a ZQ calibration circuit connected to the signal pin and configured to perform calibration using a VOH target level of the signal pin and control a termination resistance of the signal pin.

    Quantum dot device and electronic device

    公开(公告)号:US12225747B2

    公开(公告)日:2025-02-11

    申请号:US18512352

    申请日:2023-11-17

    Abstract: A quantum dot device including an anode and a cathode, a light emitting layer disposed between the anode and the cathode, the light emitting layer comprising quantum dots, a first hole auxiliary layer disposed on the anode, the first hole auxiliary layer including poly(3,4-ethylenedioxythiophene)-polystyrenesulfonate or a derivative thereof (PEDOT:PSS), a second hole auxiliary layer disposed on the first hole auxiliary layer and including a hole transport material different from the PEDOT:PSS, wherein the light emitting layer is disposed on the second hole auxiliary layer, wherein the first hole auxiliary layer has a first surface facing the anode and a second surface facing the second hole auxiliary layer, and the second surface includes a surface modification region including a surface modification material having a carboxylic acid group, a phosphonic acid group, a sulfonic acid group, or a salt thereof. An electronic device that includes the quantum dot device.

    Integrated circuit including gate-all-around transistor

    公开(公告)号:US12046653B2

    公开(公告)日:2024-07-23

    申请号:US17501454

    申请日:2021-10-14

    CPC classification number: H01L29/42392 H01L27/0924 H01L29/0673 H10B10/12

    Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

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