公开(公告)号：US20220020753A1

公开(公告)日：2022-01-20

申请号：US17185102

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun JUNG ,  Heon Jong SHIN ,  Min Chan GWAK ,  Sung Moon LEE ,  Jeong Ki HWANG

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US20230403839A1

公开(公告)日：2023-12-14

申请号：US18455980

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun JUNG ,  Heon Jong SHIN ,  Min Chan GWAK ,  Sung Moon LEE ,  Jeong Ki HWANG

IPC: H10B10/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B10/12 ,  H01L23/528 ,  H01L21/76802 ,  H01L21/76883 ,  H10B10/125

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.