公开(公告)号：US20240203831A1

公开(公告)日：2024-06-20

申请号：US18486416

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Jin Kyu KIM ,  Sang Cheol NA ,  Yun Suk NAM ,  Kyoung Woo LEE ,  Hidenobu FUKUTOME

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a power delivery network layer; an insulating layer on the power delivery network layer and having an opening therein; a semiconductor layer filling the opening and covering the insulating layer; a first through-via extending through the semiconductor layer and electrically connected to the power delivery network layer; a second through-via extending through the insulating layer and the semiconductor layer and electrically connected to the power delivery network layer; a logic element on the semiconductor layer and electrically connected to the first through-via; and a passive element on the semiconductor layer and electrically connected to the second through-via.

公开(公告)号：US20240047463A1

公开(公告)日：2024-02-08

申请号：US18131548

申请日：2023-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Hoon HWANG ,  Seung Min SONG ,  Min Chan GWAK

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L21/823481

Abstract: In some embodiments, a semiconductor device includes a first active pattern extended in a first horizontal direction on a substrate, a second active pattern extended in the first horizontal direction on the substrate, a first bottom gate electrode extended in a second horizontal direction on the first active pattern, a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode, a second bottom gate electrode extended in the second horizontal direction on the second active pattern, a second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, and a first gate cut comprising a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode. A width of the second portion exceeds a width of the first portion.

公开(公告)号：US20250132257A1

公开(公告)日：2025-04-24

申请号：US18650306

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin KIM ,  Dong Hoon HWANG ,  Min Chan GWAK

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: A semiconductor device may include a via pattern connected to a conductive pattern on a substrate, the via pattern including a lower via pattern and an upper via pattern stacked on the lower via pattern, and a wiring line connected to the upper via pattern and extending in a second direction. The wiring line may include a same metal as the upper via pattern. A bottom width of the wiring line may be greater than a top width of the wiring line. a widths of an upper face of the lower via pattern may be equal to width of the bottom face of the upper via pattern.

公开(公告)号：US20220020753A1

公开(公告)日：2022-01-20

申请号：US17185102

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun JUNG ,  Heon Jong SHIN ,  Min Chan GWAK ,  Sung Moon LEE ,  Jeong Ki HWANG

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US20210020509A1

公开(公告)日：2021-01-21

申请号：US17031279

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan GWAK ,  Hwi Chan JUN ,  Heon Jong SHIN ,  So Ra YOU ,  Sang Hyun LEE ,  In Chan HWANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20230403839A1

公开(公告)日：2023-12-14

申请号：US18455980

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun JUNG ,  Heon Jong SHIN ,  Min Chan GWAK ,  Sung Moon LEE ,  Jeong Ki HWANG

IPC: H10B10/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B10/12 ,  H01L23/528 ,  H01L21/76802 ,  H01L21/76883 ,  H10B10/125

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US20230326831A1

公开(公告)日：2023-10-12

申请号：US18127895

申请日：2023-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Anthony Dongick LEE

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L23/481 ,  H01L29/66545 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

公开(公告)号：US20200126858A1

公开(公告)日：2020-04-23

申请号：US16724483

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan GWAK ,  Hwi Chan JUN ,  Heon Jong SHIN ,  So Ra YOU ,  Sang Hyun LEE ,  In Chan HWANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20190279930A1

公开(公告)日：2019-09-12

申请号：US16420825

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUL KI HONG ,  Heon Jong SHIN ,  Hwi Chan JUN ,  Min Chan GWAK

IPC: H01L23/522 ,  H01L29/06 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L29/78 ,  H01L23/485 ,  H01L21/321 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.