公开(公告)号：US20250056843A1

公开(公告)日：2025-02-13

申请号：US18438920

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Min SHIN ,  Heon Jong SHIN ,  June Young PARK ,  Jae Ran JANG ,  Sang Hee LEE ,  Kerm RIM ,  Sung Gyu HAN

IPC: H01L29/786 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes: a lower interlayer insulating layer; first and second active patterns on the lower interlayer insulating layer; a gate electrode on the first and second active patterns; a first source region on a first side of the gate electrode; a second source region on a second side of the gate electrode; a third source region on the first side of the gate electrode; a drain region on the second side of the gate electrode; a first contact adjacent to the gate electrode, and connected to the first and third source regions; a second contact adjacent to the gate electrode, and connected to the second source region; a third contact adjacent to the gate electrode, and connected to the drain region; a lower wiring layer inside the lower interlayer insulating layer; and a through via connecting the lower wiring layer with the first contact.

公开(公告)号：US20240162120A1

公开(公告)日：2024-05-16

申请号：US18205814

申请日：2023-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kern RIM ,  Doo Hyun LEE ,  Heon Jong SHIN ,  Jin Young PARK

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes first through third active patterns extending in and spaced apart from each other along a first direction on a first surface of a substrate; a first gate electrode extending in a second direction on the first active pattern; a first active cut between the first and second active patterns, wherein the first active cut extends in the second direction, and the first active cut is spaced apart from the first gate electrode in the first direction; a second active cut between the second and third active patterns, wherein the second active cut extends in the second direction, and the second active cut is spaced apart from the first active cut in the first direction; and a first through via extending vertically through the second active pattern between the first and second active cuts, and into the substrate.

公开(公告)号：US20220020753A1

公开(公告)日：2022-01-20

申请号：US17185102

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun JUNG ,  Heon Jong SHIN ,  Min Chan GWAK ,  Sung Moon LEE ,  Jeong Ki HWANG

IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US20210020509A1

公开(公告)日：2021-01-21

申请号：US17031279

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan GWAK ,  Hwi Chan JUN ,  Heon Jong SHIN ,  So Ra YOU ,  Sang Hyun LEE ,  In Chan HWANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20230403839A1

公开(公告)日：2023-12-14

申请号：US18455980

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun JUNG ,  Heon Jong SHIN ,  Min Chan GWAK ,  Sung Moon LEE ,  Jeong Ki HWANG

IPC: H10B10/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B10/12 ,  H01L23/528 ,  H01L21/76802 ,  H01L21/76883 ,  H10B10/125

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US20200126858A1

公开(公告)日：2020-04-23

申请号：US16724483

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan GWAK ,  Hwi Chan JUN ,  Heon Jong SHIN ,  So Ra YOU ,  Sang Hyun LEE ,  In Chan HWANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20190279930A1

公开(公告)日：2019-09-12

申请号：US16420825

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUL KI HONG ,  Heon Jong SHIN ,  Hwi Chan JUN ,  Min Chan GWAK

IPC: H01L23/522 ,  H01L29/06 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L29/78 ,  H01L23/485 ,  H01L21/321 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.