公开(公告)号：US11296104B2

公开(公告)日：2022-04-05

申请号：US16845236

申请日：2020-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sup Lee ,  Phil Ouk Nam ,  Sung Yun Lee ,  Chang Seok Kang

IPC: H01L27/11575 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11578

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

公开(公告)号：US10658230B2

公开(公告)日：2020-05-19

申请号：US16410268

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chung-Il Hyun ,  Semee Jang ,  Sung Yun Lee

IPC: H01L21/768 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L23/522

Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.

公开(公告)号：US11910614B2

公开(公告)日：2024-02-20

申请号：US17711826

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Sup Lee ,  Phil Ouk Nam ,  Sung Yun Lee ,  Chang Seok Kang

IPC: H10B43/50 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/50 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53295 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

公开(公告)号：US10355010B2

公开(公告)日：2019-07-16

申请号：US15295119

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Hyun You ,  Jin Taek Park ,  Taek Soo Shin ,  Sung Yun Lee

IPC: H01L29/788 ,  H01L29/792 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

公开(公告)号：US10854623B2

公开(公告)日：2020-12-01

申请号：US16509708

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Hyun You ,  Jin Taek Park ,  Taek Soo Shin ,  Sung Yun Lee

IPC: H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.