公开(公告)号：US09431476B2

公开(公告)日：2016-08-30

申请号：US15087349

申请日：2016-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108 ,  H01L21/764

CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

公开(公告)号：US09349633B2

公开(公告)日：2016-05-24

申请号：US14563269

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik Kim ,  Sung-Eui Kim ,  Hyoung-Sub Kim ,  Sung-Kwan Choi

IPC: H01L21/768 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/768 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成隔离层，其中限定有源图案，在衬底的有源图案和隔离层上形成绝缘中间层，去除绝缘层间的部分，活性图案和 所述隔离层形成第一凹部，在由所述第一凹部暴露的所述有源图案的第一区域上的所述第一凹部中形成第一接触，通过执行各向同性蚀刻来去除所述第一凹部中的所述有源图案的部分和所述隔离层 处理，以形成放大的第一凹部，并且填充放大的第一凹部以形成围绕第一接触件的侧壁的第一间隔件。

公开(公告)号：US20160225845A1

公开(公告)日：2016-08-04

申请号：US15087349

申请日：2016-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

IPC: H01L49/02

CPC classification number: H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

Abstract translation: 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。