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1.发明申请公开(公告)号：US20200050728A1
公开(公告)日：2020-02-13
申请号：US16378751
申请日：2019-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： JIN-TAE KIM , Sung-We Cho , Tae-Joong Song , Seung-Young Lee , Jin-Young Lim
Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.
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公开(公告)号：US11287474B2
公开(公告)日：2022-03-29
申请号：US16552109
申请日：2019-08-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young Kim , Sung-We Cho , Dal-Hee Lee , Jae-Ha Lee
IPC: G01R31/3185 , H03K3/3562
Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.
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3.发明授权公开(公告)号：US10990740B2
公开(公告)日：2021-04-27
申请号：US16378751
申请日：2019-04-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Tae Kim , Sung-We Cho , Tae-Joong Song , Seung-Young Lee , Jin-Young Lim
IPC: G06F30/392 , H01L27/02 , G06F30/394 , G06F30/398
Abstract: An integrated circuit may include a first standard cell including first and second active regions extending in a first horizontal direction and a first gate line extending in a second horizontal direction orthogonal to the first horizontal direction; and a second standard cell including third and fourth active regions extending in the first horizontal direction and a second gate line aligned in parallel to the first gate in the second horizontal direction and being adjacent to the first standard cell. A distance between the second active region of the first standard cell and the third active region of the second standard cell may be greater than a distance between the first and second active regions of the first standard cell, and may be greater than a distance between the third and fourth active regions of the second standard cell.
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公开(公告)号：US10216883B2
公开(公告)日：2019-02-26
申请号：US15351545
申请日：2016-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young Kim , Sung-We Cho , Tae-Joong Song
Abstract: A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.
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