公开(公告)号：US20200235126A1

公开(公告)日：2020-07-23

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young KIM ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US09905561B2

公开(公告)日：2018-02-27

申请号：US15409523

申请日：2017-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

IPC: H01L23/52 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

公开(公告)号：US09665678B2

公开(公告)日：2017-05-30

申请号：US14744178

申请日：2015-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-we Cho ,  Dal-hee Lee ,  Ha-young Kim ,  Jae-woo Seo ,  Jin-tae Kim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/505

Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

公开(公告)号：US11189639B2

公开(公告)日：2021-11-30

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young Kim ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US10651201B2

公开(公告)日：2020-05-12

申请号：US15913530

申请日：2018-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young Kim ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US20160034627A1

公开(公告)日：2016-02-04

申请号：US14744178

申请日：2015-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-we Cho ,  Dal-hee Lee ,  Ha-young Kim ,  Jae-woo Seo ,  Jin-tae Kim

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/505

Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

Abstract translation: 一种设计集成电路的方法包括处理器，其使用设计成优化性能或产量特性的多个第一标准单元接收初始定义集成电路的输入数据。 处理器替代至少一个设计用于优化不同性能或产量特性的第二标准单元，其中针对第一标准单元对应的第一标准单元优化第一标准单元。 处理器产生定义包括第二标准单元的集成电路的输出数据。 取代的第二标准单元具有与其被替代的相应的第一标准单元相同的功能。