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    Device for supporting error correction code and test method thereof
    1.
    发明授权
    Device for supporting error correction code and test method thereof 有权

    公开(公告)号：US10803971B2

    公开(公告)日：2020-10-13

    申请号：US16135325

    申请日：2018-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suk-soo Pyo ,  Hyun-taek Jung ,  Tae-joong Song

    IPC: G11C29/42 ,  G06F11/10 ,  G11C29/46 ,  G06F11/22 ,  G11C29/36 ,  G11C29/04

    Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.

    Integrated circuit and semiconductor device
    3.
    发明授权
    Integrated circuit and semiconductor device 有权

    公开(公告)号：US09905561B2

    公开(公告)日：2018-02-27

    申请号：US15409523

    申请日：2017-01-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    IPC: H01L23/52 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  G06F17/50

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    Integrated circuit including standard cell
    4.
    发明授权
    Integrated circuit including standard cell 有权

    公开(公告)号：US11239151B2

    公开(公告)日：2022-02-01

    申请号：US16886020

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum Kim ,  Ha-young Kim ,  Tae-joong Song ,  Jong-hoon Jung ,  Gi-young Yang ,  Jin-young Lim

    IPC: H01L23/50 ,  H01L29/788 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L23/498

    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

    Integrated circuit including standard cell
    6.
    发明授权
    Integrated circuit including standard cell 有权

    公开(公告)号：US10354947B2

    公开(公告)日：2019-07-16

    申请号：US15871206

    申请日：2018-01-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum Kim ,  Ha-young Kim ,  Tae-joong Song ,  Jong-hoon Jung ,  Gi-young Yang ,  Jin-young Lim

    IPC: H01L23/50 ,  H01L29/788 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L23/498

    Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

    METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT
    7.
    发明申请
    METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT 有权
    集成电路布局的设计方法和制造集成电路的方法

    公开(公告)号：US20160055286A1

    公开(公告)日：2016-02-25

    申请号：US14820983

    申请日：2015-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-hoon Baek ,  Tae-joong Song ,  Sang-kyu Oh ,  Seung-young Lee

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G03F1/00 ,  G06F17/5072 ,  G06F17/5081 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

    Abstract: A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced.

    Abstract translation: 设计集成芯片（IC）的布局的方法包括通过放置和布线定义IC的多个标准单元来设计第一布局，以及通过在与...相关的掩模数据准备处理过程中修改第一布局来生成第二布局 第一布局，其中通过连接与第一布局的第一层相对应的第一层图案中的第一和第二图案来生成第二布局，使得形成第一层图案所需的掩模的数量减少。

    Integrated circuit including standard cell
    8.
    发明授权
    Integrated circuit including standard cell 审中-公开

    公开(公告)号：US10672702B2

    公开(公告)日：2020-06-02

    申请号：US16433092

    申请日：2019-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-gyum Kim ,  Ha-young Kim ,  Tae-joong Song ,  Jong-hoon Jung ,  Gi-young Yang ,  Jin-young Lim

    IPC: H01L23/50 ,  H01L29/788 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L23/498

    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

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