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    Method and program for designing integrated circuit
    2.
    发明授权
    Method and program for designing integrated circuit 有权

    公开(公告)号：US09665678B2

    公开(公告)日：2017-05-30

    申请号：US14744178

    申请日：2015-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-we Cho ,  Dal-hee Lee ,  Ha-young Kim ,  Jae-woo Seo ,  Jin-tae Kim

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/505

    Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

    Methods of generating integrated circuit layout using standard cell library
    4.
    发明授权
    Methods of generating integrated circuit layout using standard cell library 有权

    公开(公告)号：US10108772B2

    公开(公告)日：2018-10-23

    申请号：US15271883

    申请日：2016-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-hoon Baek ,  Jae-woo Seo ,  Gi-young Yang ,  Dal-hee Lee ,  Sung-wee Cho

    IPC: G06F17/50 ,  H01L29/66 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

    Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

    Methods of generating integrated circuit layout using standard cell library
    5.
    发明授权
    Methods of generating integrated circuit layout using standard cell library 有权
    使用标准单元库生成集成电路布局的方法

    公开(公告)号：US09460259B2

    公开(公告)日：2016-10-04

    申请号：US14832325

    申请日：2015-08-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-hoon Baek ,  Jae-woo Seo ,  Gi-young Yang ,  Dal-hee Lee ,  Sung-wee Cho

    IPC: G06F17/50 ,  H01L21/8234 ,  H01L21/8238

    CPC classification number: G06F17/5072 ,  G06F17/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/12 ,  G06F2217/78 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/6681

    Abstract: Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

    Abstract translation: 生成集成电路布局的方法包括通过提供与第一单元边界线相邻的第一有源区来形成标准单元。 第一有效区域与第一细胞边界线隔开第一距离。 第二活动区域被设置成与第二单元边界线相邻。 第二细胞边界线与第一细胞边界线相反。 第二有效区域与第二细胞边界线间隔第二距离。 翅片形成在第一和第二活动区域上。 翅片在第一方向上延伸并且在基本上垂直于第一方向的第二方向上彼此平行。 第一个细胞边界线平行于翅片。 当第一和第二有效区域上的多个翅片改变时，第一距离和第二距离保持恒定。

    METHOD AND PROGRAM FOR DESIGNING INTEGRATED CIRCUIT
    7.
    发明申请
    METHOD AND PROGRAM FOR DESIGNING INTEGRATED CIRCUIT 有权
    设计集成电路的方法与程序

    公开(公告)号：US20160034627A1

    公开(公告)日：2016-02-04

    申请号：US14744178

    申请日：2015-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-we Cho ,  Dal-hee Lee ,  Ha-young Kim ,  Jae-woo Seo ,  Jin-tae Kim

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/505

    Abstract: A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

    Abstract translation: 一种设计集成电路的方法包括处理器，其使用设计成优化性能或产量特性的多个第一标准单元接收初始定义集成电路的输入数据。 处理器替代至少一个设计用于优化不同性能或产量特性的第二标准单元，其中针对第一标准单元对应的第一标准单元优化第一标准单元。 处理器产生定义包括第二标准单元的集成电路的输出数据。 取代的第二标准单元具有与其被替代的相应的第一标准单元相同的功能。

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