NON-VOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF

    公开(公告)号:US20230154542A1

    公开(公告)日:2023-05-18

    申请号:US17984890

    申请日:2022-11-10

    CPC classification number: G11C16/14 G11C16/08 G11C16/24

    Abstract: A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.

    Image processing device for controlling pixel output level and operating method thereof

    公开(公告)号:US12170856B2

    公开(公告)日:2024-12-17

    申请号:US17823125

    申请日:2022-08-30

    Abstract: An image sensor includes a pixel array that includes a first pixel group located in a first row and including a first select transistor and a first floating diffusion region, a second pixel group located in a second row and including a second select transistor and a second floating diffusion region, and a column line connected to both the first pixel group and the second pixel group. While charges generated by a photoelectric conversion element of the first pixel group are transferred to the first floating diffusion region, the first select transistor is turned off, the second select transistor is turned on, and a first voltage is applied to the column line through the second select transistor. A photoelectric conversion element of the second pixel group generates charges prior to the photoelectric conversion element of the first pixel group, so as to be transferred to the second floating diffusion region.

    Method of testing a suspend operation

    公开(公告)号:US12039186B2

    公开(公告)日:2024-07-16

    申请号:US17875569

    申请日:2022-07-28

    CPC classification number: G06F3/0653 G06F3/0604 G06F3/0679

    Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM

    公开(公告)号:US20250103513A1

    公开(公告)日:2025-03-27

    申请号:US18601839

    申请日:2024-03-11

    Abstract: A nonvolatile memory device includes a memory cell array to store an original setting data, a page buffer circuit connected to the memory cell array through a plurality of bit-lines, a secure buffer and a control circuit. The secure buffer includes an access control circuit and a plurality registers with restricted access, and the plurality registers store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the secure buffer. The plurality registers include a first register and second registers. The access control circuit, in response to the first register being accessed, accesses at least a portion of the second registers concurrently with accessing the first register.

    METHOD OF TESTING A SUSPEND OPERATION
    5.
    发明公开

    公开(公告)号:US20230143341A1

    公开(公告)日:2023-05-11

    申请号:US17875569

    申请日:2022-07-28

    CPC classification number: G06F3/0653 G06F3/0604 G06F3/0679

    Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

Patent Agency Ranking