公开(公告)号：US11915770B2

公开(公告)日：2024-02-27

申请号：US17736395

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minseok Kim ,  Junyong Park ,  Doohyun Kim ,  Ilhan Park

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C29/10 ,  G11C16/16

CPC classification number: G11C16/3495 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C29/10 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: In a method of reducing reliability degradation of a nonvolatile memory device, the nonvolatile memory device in which initial data having an initial threshold voltage distribution is stored in a plurality of memory cells connected to a plurality of wordlines is provided. Before a first process causing reliability degradation is performed, a first write operation is performed such that first data having a first threshold voltage distribution is stored into memory cells connected to first wordlines. The first wordlines have a degree of reliability degradation less than a reference value. Before the first process is performed, a second write operation is performed such that second data having a second threshold voltage distribution is stored into memory cells connected to second wordlines. The second wordlines have a degree of reliability degradation greater than or equal to the reference value.

公开(公告)号：US11972111B2

公开(公告)日：2024-04-30

申请号：US18052350

申请日：2022-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyong Park ,  Minseok Kim ,  Jisu Kim ,  Ilhan Park ,  Doohyun Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

公开(公告)号：US11869512B2

公开(公告)日：2024-01-09

申请号：US17492267

申请日：2021-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyong Park ,  Jiyeon Ma ,  Donghun Shin ,  Youngah Lee ,  Daewung Kim ,  Sungdo Son ,  Dahye Shim ,  Hyungmin Yook

IPC: G10L17/06 ,  G06F3/0481 ,  G10L17/22

CPC classification number: G10L17/06 ,  G06F3/0481 ,  G10L17/22

Abstract: An electronic device and a control method thereof are provided. The electronic apparatus includes a voice input unit, a display, a memory storing at least one instruction, and a processor configured to execute the at least one instruction. The processor is configured to: based on a voice of a user being input through the voice input unit, recognize the user who has uttered the voice by comparing the voice with a plurality of pre-registered voices; and control the display to display an indicator corresponding to the recognized user.

公开(公告)号：US20230146741A1

公开(公告)日：2023-05-11

申请号：US18052350

申请日：2022-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyong Park ,  Minseok Kim ,  Jisu Kim ,  Ilhan Park ,  Doohyun Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

公开(公告)号：US20230143341A1

公开(公告)日：2023-05-11

申请号：US17875569

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suyong Kim ,  Junyong Park ,  Sangbum Yun ,  Ilhan Park

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.

公开(公告)号：US11901021B2

公开(公告)日：2024-02-13

申请号：US17530586

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyong Park ,  Hyunggon Kim ,  Byungsoo Kim ,  Sungmin Joe

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C11/56 ,  G06F3/06 ,  G11C16/10 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H10B43/27 ,  G11C2211/5621

Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

公开(公告)号：US20230154542A1

公开(公告)日：2023-05-18

申请号：US17984890

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Park ,  Minseok Kim ,  Junyong Park ,  Suyong Kim ,  Ilhan Park

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C16/08 ,  G11C16/24

Abstract: A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.

公开(公告)号：US12300334B2

公开(公告)日：2025-05-13

申请号：US18400297

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyong Park ,  Hyunggon Kim ,  Byungsoo Kim ,  Sungmin Joe

IPC: G11C16/04 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  H10B43/27

Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

公开(公告)号：US12075624B2

公开(公告)日：2024-08-27

申请号：US17378317

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokcheon Baek ,  Younghwan Son ,  Miram Kwon ,  Junyong Park ,  Jiho Lee

IPC: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: Provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other on the first substrate, and an end portion of the first electrode layer and an end portion of the second electrode layer are offset from each other on the connection region; a first cell contact penetrating the second electrode layer and the first electrode layer such as to be connected to the second electrode layer on the connection region; and a first contact dielectric pattern between the first cell contact and the first electrode layer. The first cell contact includes columnar part that vertically extends from a top surface of the first substrate, and a connection part that laterally protrudes from the columnar part and contacts the second electrode layer.

公开(公告)号：US12039186B2

公开(公告)日：2024-07-16

申请号：US17875569

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyong Kim ,  Junyong Park ,  Sangbum Yun ,  Ilhan Park

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method of testing a suspend operation, the method including: determining whether to transfer a suspend sampling signal to a suspend command circuit at a time point prior to each of a plurality of suspend operation time points stored in a sequence operation circuit; transferring the suspend sampling signal from the sequence operation circuit to the suspend command circuit; generating an internal suspend operation command based on the suspend sampling signal; transferring the internal suspend operation command from the suspend command circuit to the sequence operation circuit; performing suspend operations for all the plurality of suspend operation time points in response to the internal suspend operation command; and determining whether the suspend operations are performed at all of the suspend operation time points.