公开(公告)号：US12033855B2

公开(公告)日：2024-07-09

申请号：US17322412

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Hoon Kim ,  Soo Kyung Kim ,  Tae-Kyu Kim ,  Young Kuk Byun ,  Woo Jin Jung

IPC: H01L21/027 ,  H01L21/311

CPC classification number: H01L21/0274 ,  H01L21/31144

Abstract: A method of manufacturing a semiconductor device includes forming a mold layer on a semiconductor wafer having a plurality of integrated circuit die at least partially defined therein. An etch stopper film is selectively formed on a second portion of the mold layer extending adjacent a periphery of the semiconductor wafer, but not on a first portion of the mold layer extending opposite at least one of the plurality of integrated circuit die. A preliminary pattern layer is formed on the etch stopper film and on the first portion of the mold layer. A plurality of patterns are formed in the preliminary pattern layer by selectively exposing the preliminary pattern layer to extreme ultraviolet light (EUV). Then, hole patterns are selectively formed in the first portion of the mold layer, using the exposed preliminary pattern layer and the etch stopper film as an etching mask.

公开(公告)号：USD892134S1

公开(公告)日：2020-08-04

申请号：US29662383

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Designer： Eena Kim ,  Tae-Kyu Kim ,  Won-Kyoung Seo ,  Jun-Hyeok Jang

公开(公告)号：US11217457B2

公开(公告)日：2022-01-04

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Kim ,  Byung-Hyun Lee ,  Yoonyoung Choi ,  Tae-Kyu Kim ,  Heesook Cheon ,  Bo-Wo Choi ,  Hyun-Sil Hong

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/48

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.

公开(公告)号：US12068157B2

公开(公告)日：2024-08-20

申请号：US17385069

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Seung Ha ,  Jang Hoon Kim ,  Tae-Kyu Kim ,  Young Kuk Byun ,  Jong Hyun Jung

IPC: H01L21/027 ,  G03F7/00 ,  G03F7/20 ,  H01L21/66

CPC classification number: H01L21/0274 ,  G03F7/70633 ,  H01L22/12

Abstract: A method of manufacturing a semiconductor device includes forming a first lower overlay key including first and second patterns in a lower layer, forming a first upper overlay key including third and fourth patterns in an upper layer vertically disposed on the lower layer, irradiating a first measurement light to a first region of interest (ROI) over first portions of the first and second patterns to detect a first overlay error and irradiating a second measurement light to a second ROI over second portions of the first and second patterns, the second ROI being different from the first ROI, to detect a second overlay error.

公开(公告)号：US20220093393A1

公开(公告)日：2022-03-24

申请号：US17322412

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Hoon Kim ,  Soo Kyung Kim ,  Tae-Kyu Kim ,  Young Kuk Byun ,  Woo Jin Jung

IPC: H01L21/027 ,  H01L21/311

Abstract: A method of manufacturing a semiconductor device includes forming a mold layer on a semiconductor wafer having a plurality of integrated circuit die at least partially defined therein. An etch stopper film is selectively formed on a second portion of the mold layer extending adjacent a periphery of the semiconductor wafer, but not on a first portion of the mold layer extending opposite at least one of the plurality of integrated circuit die. A preliminary pattern layer is formed on the etch stopper film and on the first portion of the mold layer. A plurality of patterns are formed in the preliminary pattern layer by selectively exposing the preliminary pattern layer to extreme ultraviolet light (EUV). Then, hole patterns are selectively formed in the first portion of the mold layer, using the exposed preliminary pattern layer and the etch stopper film as an etching mask.