公开(公告)号：US11217457B2

公开(公告)日：2022-01-04

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Kim ,  Byung-Hyun Lee ,  Yoonyoung Choi ,  Tae-Kyu Kim ,  Heesook Cheon ,  Bo-Wo Choi ,  Hyun-Sil Hong

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/48

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.

公开(公告)号：US09620364B2

公开(公告)日：2017-04-11

申请号：US14715631

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sil Hong ,  Sungil Cho

IPC: H01L21/033 ,  H01L21/31 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/0332 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0334 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a molding layer and a supporter layer on a semiconductor substrate, forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer. The first mask layer is formed of a material having an etch selectivity with respect to the molding layer and the second mask layer is formed of a material having an etch selectivity with respect to the supporter layer. The method includes forming a first mask pattern and a second mask pattern formed on the first mask pattern by patterning the multiple mask layer, etching the supporter layer by performing a first etching process using the second mask pattern as an etch mask, etching the molding layer, and forming a hole by performing a second etching process using the first mask pattern as an etch mask.

公开(公告)号：US12237208B2

公开(公告)日：2025-02-25

申请号：US17668452

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Ki-Jeong Kim ,  Hwan Lim ,  Hyun-Sil Hong

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H10B12/00 ,  H01L21/311

Abstract: A semiconductor device includes a substrate having one or more inner surfaces defining trenches that define an active pattern of the substrate, the trenches including a first trench and a second trench which have different widths, a device isolation layer on the substrate such that the device isolation layer at least partially fills the trenches, and a word line intersecting the active pattern. The device isolation layer includes a first isolation pattern covering a portion of the second trench, a second isolation pattern on the first isolation pattern and covering a remaining portion of the second trench, and a filling pattern filling the first trench under the word line. A top surface of the second isolation pattern is located at a higher level than a top surface of the filling pattern.