公开(公告)号：US20240379795A1

公开(公告)日：2024-11-14

申请号：US18504981

申请日：2023-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok PARK ,  Taehyun RYU ,  Namhyun LEE

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device comprising: a substrate; a first lower pattern on the substrate; a second lower pattern on the first lower pattern; channel patterns on the second lower pattern; a first field insulating layer on a first side surface of the first lower pattern; a second field insulating layer on a second side surface of the first lower pattern; a buried insulating structure on the first field insulating layer and on side surfaces of the channel patterns; a protective layer on the second field insulating layer; source/drain patterns on sides of each of the channel patterns; and a gate electrode extending around the channel patterns and the buried insulating structure, wherein the protective layer comprises: a protective insulating layer between the first lower pattern and the second lower pattern, and between the gate electrode and the second field insulating layer; and a protective liner extending around the protective insulating layer.

公开(公告)号：US20250072066A1

公开(公告)日：2025-02-27

申请号：US18412812

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooseok PARK ,  Wookhwan SONG ,  Donghoon HWANG ,  Myungil KANG ,  Taehyun RYU ,  Namhyun LEE

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a first active pattern, a second active pattern spaced apart at a first distance from the first active pattern, a third active pattern spaced apart at a second distance from the second active pattern, a first device isolation layer between the first and second active patterns, a second device isolation layer between the second and third active patterns, a first channel structure overlapping the first active pattern, a second channel structure overlapping the second active pattern, a third channel structure overlapping the third active pattern, and a separation dielectric layer between the first and second channel structures. The separation dielectric layer may overlap the first device isolation layer. A level of a top surface of the first device isolation layer may be higher than a level of a top surface of the second device isolation layer.