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1.发明授权公开(公告)号：US11881866B2
公开(公告)日：2024-01-23
申请号：US17879543
申请日：2022-08-02
CPC分类号： H03L7/099 , H03K5/01 , H03K19/21 , H03K2005/00078
摘要： An electronic device and a method of controlling a slew rate for high-speed data communications are provided. The electronic device, according to an embodiment of the disclosure, includes a serializer configured to receive parallel data from another electronic device along with clock rate information, and convert the parallel data into serial data. The electronic device further includes a delay generator configured to generate a delay in the converted serial data using the clock rate information. The electronic device further includes a multiplexer configured to multiplex the converted serial data of the non-slew mode with the delayed data of the slew mode. The electronic device further includes a plurality of driver legs configured to receive the multiplexed data, and transfer the multiplexed data to the another electronic device. The electronic device further includes at least one of a voltage-controlled oscillator and a current-controlled oscillator configured to generate the clock rate information.
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公开(公告)号：US12095458B2
公开(公告)日：2024-09-17
申请号：US17825378
申请日：2022-05-26
IPC分类号： H03K19/0185 , H03K19/017 , H03K19/094 , H03K19/20
CPC分类号： H03K19/01855 , H03K19/01742 , H03K19/0941 , H03K19/20
摘要： A method, implemented in a serializer for quarter rate serialization, is disclosed. The method includes receiving a plurality of in-phase and quarter-phase clock signals defining a quarter phase clock. The method includes receiving a quarter rate data input and sequentially outputting data in accordance with the quarter phase clock. The method includes receiving at least one data input from amongst the quarter rate input and outputting a first logical output in accordance with the in-phase clock signal and the quarter-phase clock signal. The method includes receiving said at least one data input and outputting a second logical output in accordance a complementary in-phase clock signal and a complementary quarter-phase clock signal. The method includes outputting, an output associated with the branch.
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公开(公告)号：US10804904B1
公开(公告)日：2020-10-13
申请号：US16725580
申请日：2019-12-23
摘要： A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits. Each serializer circuit generates a sampled sync loss signal by sampling the sync loss pulse in accordance with a parallel clock signal, and a Boolean value is assigned to the sampled sync loss signal and output. A logic block detects a sync loss when the sampled sync loss signal of any serializer circuit is out of sync from the sync loss pulse based on the Boolean value.
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公开(公告)号：US11979263B2
公开(公告)日：2024-05-07
申请号：US17872258
申请日：2022-07-25
CPC分类号： H04L25/03878 , H04B3/06 , H04B17/14
摘要： A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.
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5.发明授权公开(公告)号：US11303278B1
公开(公告)日：2022-04-12
申请号：US17222349
申请日：2021-04-05
IPC分类号： H03K3/00 , H03K19/0175 , H03K19/0185 , H03L5/00 , H03K3/356
摘要： The present disclosure relates to a circuit for level shifting of a data voltage from a transmitter. The circuit comprises an inverter logic. The inverter logic comprises a first transistor and a second transistor. The first transistor is connected to a source voltage and the second transistor is connected to ground. A capacitor is connected to an input of the first transistor and configured to drive the first transistor. The capacitor is configured to charge to a charged voltage equivalent to a difference between the source voltage and the data voltage. The second transistor is configured to be driven by the data voltage, thereby level shifting a level of the data voltage to a level of the source voltage.
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公开(公告)号：US10892775B1
公开(公告)日：2021-01-12
申请号：US16796232
申请日：2020-02-20
摘要： Various example embodiments relate to unifying a plurality of parallel interfaces. A transmitting apparatus configured to serialize parallel bits implements a dynamic divider circuit for loading varying parallel bits into the transmitting apparatus. An input clock generator is configured to generate a desired and/or predefined clock frequency. The dynamic divider circuit receives the desired and/or predefined clock frequency and generates a parallel clock frequency by dividing the desired and/or predefined clock frequency based on a variable division input. Number of parallel bits loaded into the transmitting apparatus is based on the generated parallel clock frequency. Further, a shift register generates a bit stream from the parallel bits loaded into the shift register and the generated bit stream is converted to serial bit by a multiplexer.
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