公开(公告)号：US10262753B2

公开(公告)日：2019-04-16

申请号：US15165312

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ungjin Jang

IPC: G01R31/26 ,  G11C29/56 ,  G01R31/319 ,  G11C29/26

Abstract: The test board may include sockets in which a plurality of devices-under-test (DUTs) is inserted, and an auxiliary test device connection tree electrically connected to the sockets. The auxiliary test device connection tree includes at least one first auxiliary test device receiving and outputting a test request from an external apparatus, and at least one second auxiliary test device generating a test clock and a test pattern in response to the test request outputted from the at least one first auxiliary test device, performing a test operation about at least one among the DUTs using the generated test pattern, and outputting whether or not of an error of the test operation to the at least one first auxiliary test device.

公开(公告)号：US20250044353A1

公开(公告)日：2025-02-06

申请号：US18635088

申请日：2024-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ungjin Jang ,  Hyucksoo Jeon

IPC: G01R31/317 ,  G01R31/319

Abstract: Provided are a semiconductor test apparatus for simultaneously testing a maximum number of semiconductor chips, and a power supply method of the semiconductor test apparatus. The semiconductor test apparatus includes a tester including a power supply configured to simultaneously supply power to a plurality of devices under test (DUTs) during a test, and a test board arranged between the tester and the plurality of DUTs and transmitting the power from the power supply to the tester, wherein the power supply includes a plurality of power channels, and each of the plurality of DUTs receive two or more types of power from the power channels, each type of power being power supplied at a respective supply voltage for the DUT, the power supply shares current between the plurality of power channels and supplies the shared current amount to each of the plurality of DUTs.

公开(公告)号：US12111351B2

公开(公告)日：2024-10-08

申请号：US17522188

申请日：2021-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ungjin Jang ,  Seonggwon Jang ,  Yongjeong Kim ,  Sooyong Park

IPC: G11C29/56 ,  G01R31/317 ,  G01R31/319 ,  G11C29/08

CPC classification number: G01R31/31702 ,  G01R31/31905 ,  G11C29/08 ,  G11C29/56 ,  G11C2029/5602

Abstract: A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.