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    Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array
    4.
    发明授权
    Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array 失效
    防止从编程的现场可编程门阵列读出一些而不是其他信息的安全反熔丝

    公开(公告)号：US5898776A

    公开(公告)日：1999-04-27

    申请号：US754461

    申请日：1996-11-21

    申请人： James M. Apland ,  David D. Eaton ,  Andrew K. Chan

    发明人： James M. Apland ,  David D. Eaton ,  Andrew K. Chan

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  H04L9/00

    CPC分类号： G01R31/318519 ,  G01R31/31719 ,  G01R31/318555 ,  G01R31/31702 ,  G01R31/318558

    摘要： A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.

    摘要翻译： 现场可编程门阵列具有安全反熔丝，其在编程时防止读出指示互连结构如何编程的数据，但是不防止读出指示哪个其它反熔丝被编程的数据。 在一些实施例中，当安全反熔丝被编程但是与现场可编程门阵列的顶侧和底侧相邻的编程控制移位寄存器未被禁用时，与左侧和右侧相邻的编程控制移位寄存器被禁用， 。 还提供了第二个安全反熔丝，当编程时禁用JTAG边界扫描寄存器，但不禁用JTAG旁路寄存器。 因此，信息可以通过JTAG测试电路转移，而不允许JTAG电路提取指示互连结构如何编程的信息。 提供逻辑模块和接口单元扫描路径，并支持特殊测试指令，允许将测试向量加载到逻辑模块和接口单元扫描路径中。

    Method and system for creating dipole moment model
    5.
    发明授权
    Method and system for creating dipole moment model 有权

    公开(公告)号：US12105142B2

    公开(公告)日：2024-10-01

    申请号：US17659012

    申请日：2022-04-13

    申请人： Realtek Semiconductor Corporation

    发明人： Min-Hsu Tsai ,  Ruey-Beei Wu

    IPC分类号： G01V3/10 ,  G01R31/317 ,  H01Q7/00 ,  H04B5/73

    CPC分类号： G01R31/31702 ,  H01Q7/00 ,  H04B5/73

    摘要： The present disclosure provides a method and system for creating dipole moment model. The method is applied to a tested circuit and includes: performing a near-field measurement on the tested circuit, to obtain a near-field electric field and a near-field magnetic field related to the tested circuit; performing a two-dimensional divergence calculation on the near-field electric field and the near-field magnetic field, to obtain a near-field electric divergence field and a near-field magnetic divergence field; performing a convolution calculation on the near-field electric divergence field and the near-field magnetic divergence field with a digital filter; and building a dipole moment matrix equivalent to the tested circuit according to a result of the convolution calculation.

    Detecting a Function Section in a Representation of a Quantum Circuit
    6.
    发明公开
    Detecting a Function Section in a Representation of a Quantum Circuit 审中-公开

    公开(公告)号：US20240044973A1

    公开(公告)日：2024-02-08

    申请号：US17817397

    申请日：2022-08-04

    申请人： Classiq Technologies LTD.

    发明人： Amir Haveh ,  Shmuel Ur ,  Eyal Cornfeld ,  Ofek Kirzner ,  Nir Minerbi

    IPC分类号： G01R31/317 ,  G06N10/40

    CPC分类号： G01R31/31702 ,  G06N10/40

    摘要： A method, apparatus, and product comprising: obtaining a representation of a quantum circuit; determining that a qubit is a candidate auxiliary qubit by estimating that a state of the qubit at a first cycle is identical to a state of the qubit at a second cycle; identifying a function section in the quantum circuit based on the qubit, the function section commencing at a beginning cycle, the beginning cycle is ordered before the second cycle, the function section ending at an ending cycle, the ending cycle is ordered after the first cycle, the ending cycle is ordered after the commencing cycle, the function section utilizing the qubit as an auxiliary qubit; and outputting an indication of the function section.

    Device and method for testing magnetic switches at wafer-level stage of manufacture
    8.
    发明授权
    Device and method for testing magnetic switches at wafer-level stage of manufacture 有权
    在晶圆级制造阶段测试磁性开关的装置和方法

    公开(公告)号：US08451016B2

    公开(公告)日：2013-05-28

    申请号：US12650257

    申请日：2009-12-30

    申请人： Ravi Shankar ,  Olivier Le Neel

    发明人： Ravi Shankar ,  Olivier Le Neel

    IPC分类号： G01R31/20 ,  G01R31/00 ,  G01R1/073

    CPC分类号： G01R1/07378 ,  G01R1/07342 ,  G01R31/31702 ,  G01R31/318511 ,  G01R31/3278

    摘要： A testing mechanism for testing magnetically operated microelectromechanical system (MEMS) switches at a wafer level stage of manufacture includes an electromagnetic fixture configured to be received in a standard probe ring. The electromagnetic fixture is rotatable, relative to the probe ring, to permit adjustment of orientation of a generated magnetic field relative to the MEMS devices of a subject wafer. The testing mechanism also includes a probe card with probes positioned to contact test pads on the subject wafer. During operation, the probe card is positioned over the wafer to be tested, with the test probes in electrical contact with respective contact pads of the wafer, and the electromagnetic fixture is positioned above the probe card. An electrical potential is applied across the switches on the subject wafer, and the electromagnetic fixture is energized at selected levels of power and duration. Current flow across each switch is measured to determine one or more of: open circuit contact resistance, closed circuit contact resistance, response time, response to switching magnetic field, frequency response, current capacity, critical dimensions, critical angles of magnetic field orientation, etc. Wafer level testing enables rejection of non-compliant switches before the cutting and packaging levels of manufacture.

    摘要翻译： 用于在晶片级制造阶段测试磁操作微机电系统（MEMS）开关的测试机构包括被配置为接收在标准探针环中的电磁夹具。 电磁夹具相对于探针环可旋转，以允许相对于目标晶片的MEMS器件调整产生的磁场的取向。 测试机构还包括具有探针的探针卡，所述探针被定位成接触主体晶片上的测试焊盘。 在操作期间，探针卡位于要测试的晶片上，测试探针与晶片的相应接触焊盘电接触，并且电磁夹具位于探针卡上方。 在主体晶片上的开关上施加电势，并且电磁夹具以选定的功率和持续时间被激励。 测量每个开关上的电流，以确定以下一个或多个：开路接触电阻，闭路接触电阻，响应时间，对开关磁场的响应，频率响应，电流容量，临界尺寸，磁场定向的临界角等 晶圆级别测试在切割和封装制造水平之前能够拒绝不符合标准的开关。

    MEMS SENSOR WITH BUILT-IN SELF-TEST
    9.
    发明申请
    MEMS SENSOR WITH BUILT-IN SELF-TEST 审中-公开
    具有内置自检功能的MEMS传感器

    公开(公告)号：US20100145660A1

    公开(公告)日：2010-06-10

    申请号：US12329823

    申请日：2008-12-08

    申请人： Christoph Lang ,  Valdimir Petkov ,  Udo-Martin Gomez

    发明人： Christoph Lang ,  Valdimir Petkov ,  Udo-Martin Gomez

    IPC分类号： H03F1/26 ,  G01D18/00

    CPC分类号： G01R31/31702 ,  G01D3/08 ,  G01P21/00

    摘要： A method and system for testing a MEMS sensor element during operation of a MEMS sensor system in one embodiment includes a test signal generator configured to generate a broad frequency band test signal, and a verification signal substantially identical to the test signal, a microelectrical-mechanical system (MEMS) sensor element operatively connected to the test signal generator for generating a sensor output in response to the test signal, a comparison component configured to generate an evaluation signal output based upon the verification signal and the test signal, and an evaluation circuit operatively connected to the comparison component and configured to identify a mismatch between the verification signal and the sensor output based upon the evaluation signal.

    摘要翻译： 在一个实施例中，用于在MEMS传感器系统的操作期间测试MEMS传感器元件的方法和系统包括被配置为产生宽频带测试信号的测试信号发生器和与测试信号基本相同的验证信号，微机电 系统（MEMS）传感器元件，其可操作地连接到所述测试信号发生器，用于响应于所述测试信号产生传感器输出;比较部件，被配置为基于所述验证​​信号和所述测试信号生成评估信号输出;以及评估电路， 连接到比较部件并且被配置为基于评估信号来识别验证信号和传感器输出之间的不匹配。