公开(公告)号：US12032019B2

公开(公告)日：2024-07-09

申请号：US17582385

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjeong Kim ,  Jongjin An ,  Seonggwon Jang ,  Pilho Lee ,  Inhoon Jang

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G01R31/319 ,  H01L21/66 ,  H03K3/017 ,  H03K19/21 ,  H03L7/099

CPC classification number: G01R31/3177 ,  G01R31/2834 ,  G01R31/3004 ,  G01R31/31727 ,  G01R31/31924 ,  H03K3/017 ,  H03K19/21 ,  H03L7/099 ,  H01L22/34 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Provided are a clock conversion device, a test system including the same, and a method of operating the test system. The clock conversion device includes a first clock generator configured to receive a first input clock signal from test logic and generate a first clock signal of which a frequency is multiplied and a phase is locked; a clock conversion circuit configured to receive the first clock signal and generate one or more second clock signals by converting at least one clock characteristic of the first clock signal; and an output selector configured to output any one of the first clock signal and the one or more second clock signals as an output clock signal, wherein the clock conversion device is configured to provide the output clock signal to a device under test (DUT).

公开(公告)号：US12111351B2

公开(公告)日：2024-10-08

申请号：US17522188

申请日：2021-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ungjin Jang ,  Seonggwon Jang ,  Yongjeong Kim ,  Sooyong Park

IPC: G11C29/56 ,  G01R31/317 ,  G01R31/319 ,  G11C29/08

CPC classification number: G01R31/31702 ,  G01R31/31905 ,  G11C29/08 ,  G11C29/56 ,  G11C2029/5602

Abstract: A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.