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公开(公告)号：US10707548B2
公开(公告)日：2020-07-07
申请号：US15336042
申请日：2016-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hyun Kim , Sooyong Park
Abstract: An impedance matching device includes a tapered strip line and a plurality of strip lines. The tapered strip line extends in a first direction on a substrate and has a width in a second direction perpendicular to the first direction. The tapered strip line includes first to n-th segments having identical lengths and different widths, wherein the ‘n’ is a natural number of two or more. The plurality of strip lines are connected to the n-th segment such that an input signal received through the first segment is split.
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公开(公告)号：US12111351B2
公开(公告)日：2024-10-08
申请号：US17522188
申请日：2021-11-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ungjin Jang , Seonggwon Jang , Yongjeong Kim , Sooyong Park
IPC: G11C29/56 , G01R31/317 , G01R31/319 , G11C29/08
CPC classification number: G01R31/31702 , G01R31/31905 , G11C29/08 , G11C29/56 , G11C2029/5602
Abstract: A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.
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公开(公告)号：US20240080982A1
公开(公告)日：2024-03-07
申请号：US18372937
申请日：2023-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juho Kim , Woochul Park , Dongyeol Kwak , Juwon Kim , Yousok Min , Wonbin Jo , Sooyong Park
CPC classification number: H05K1/144 , H05K1/115 , H05K2201/042 , H05K2201/10378
Abstract: An electronic device includes a housing including a front surface, a rear surface that is opposite to the front surface, and a side surface enclosing an inner space between the front surface and the rear surface, a display that is visually exposed to the outside of the electronic device, and a printed circuit board that is in the inner space. The printed circuit board includes a plurality of circuit boards that are parallel to one another and include electrical elements and one or more interposers that are between the plurality of circuit boards and connecting a pair of circuit boards adjacent to each other in a height direction. The one or more interposers include one or more via holes, a via and one or more interposer through holes.
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公开(公告)号：US09759741B2
公开(公告)日：2017-09-12
申请号：US14863703
申请日：2015-09-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sooyong Park , Yong chul Jang , Kijae Song
CPC classification number: G01R1/0408 , G01R31/2889 , H01L2224/16225
Abstract: Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation.
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