公开(公告)号：US20190172865A1

公开(公告)日：2019-06-06

申请号：US15996480

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGHOE CHO ,  JONGBO SHIM ,  SEUNGHOON YEON ,  WON IL LEE

IPC: H01L27/146

Abstract: A method of manufacturing a semiconducor device includes providing a semiconductor substrate having a top surface, on which has been formed a color filter and a micro-lens, and a bottom surface opposite to the top surface, forming a redistribution line on the bottom surface of the semiconductor substrate, and forming on the bottom surface of the semiconductor substrate a passivation layer covering the redistribution line. After the redistribution line and passivation layer are formed, an oxide layer between the redistribution line and the passivation is formed at a temperature that avoids thermal damage to the color filter and the micro-lens.

公开(公告)号：US20240072006A1

公开(公告)日：2024-02-29

申请号：US18326554

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： WON IL LEE ,  HYUNGCHUL SHIN ,  GWANGJAE JEON ,  ENBIN JO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip including a first main region and a first edge region, and a second semiconductor chip on the first semiconductor chip and including a second main region and a second edge region. The first semiconductor chip includes a first main pad and a first dummy pad respectively on the first main region and the first edge region on a top surface of the first semiconductor chip. The second semiconductor chip includes a first semiconductor substrate, a wiring layer below the first semiconductor substrate and including a wiring dielectric layer and wiring patterns, a second main pad and a second dummy pad respectively on the second main region and the second edge region below the wiring layer. A thickness of the wiring layer is greater on the second main region than on the second edge region.

公开(公告)号：US20240234349A9

公开(公告)日：2024-07-11

申请号：US18234529

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.

公开(公告)号：US20240136311A1

公开(公告)日：2024-04-25

申请号：US18234529

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： GWANGJAE JEON ,  MINKI KIM ,  Hyungchul SHIN ,  WON IL LEE ,  HYUEKJAE LEE ,  Enbin JO

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05557 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2224/08145

Abstract: Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.