公开(公告)号：US20200212061A1

公开(公告)日：2020-07-02

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KANGYOON CHOI ,  DONG-SIK LEE ,  JONGWON KIM ,  GILSUNG LEE ,  EUNGSUK CHO ,  BYUNGYONG CHOI ,  SUNG-MIN HWANG

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.

公开(公告)号：US20210225871A1

公开(公告)日：2021-07-22

申请号：US17113456

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： DONG-SIK LEE ,  BYUNGJIN LEE ,  SUNG-MIN HWANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

公开(公告)号：US20220223619A1

公开(公告)日：2022-07-14

申请号：US17706426

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  DONG-SIK LEE ,  SUNG-MIN HWANG ,  JOON-SUNG LIM

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US20190035798A1

公开(公告)日：2019-01-31

申请号：US15954151

申请日：2018-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  DONG-SIK LEE ,  JOON-SUNG LIM

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L27/11286 ,  H01L23/53295 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/0649

Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

公开(公告)号：US20170103997A1

公开(公告)日：2017-04-13

申请号：US15285682

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOONG-SEOP LEE ,  JONGYOON CHOI ,  JINHYUN SHIN ,  DONG-SIK LEE

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/423 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L27/11582 ,  H01L21/0243 ,  H01L21/02636 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/4234 ,  H01L29/7827

Abstract: A method of fabricating a semiconductor device can include forming a channel hole in a vertical stack of alternating insulating and sacrificial layers to form a recess in a substrate. A selectively epitaxial growth can be performed to provide a lower semiconductor pattern in the recess using material of the substrate as a seed and a recess can be formed to penetrate an upper surface of the lower semiconductor pattern via the channel hole.