公开(公告)号：US20190267088A1

公开(公告)日：2019-08-29

申请号：US16059317

申请日：2018-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Hoon JEON ,  Yoo Cheol Shin ,  Jun Hee Lim ,  Sung Kweon Baek ,  Chan Ho Lee ,  Won Chul Jang ,  Sun Gyung Hwang

IPC: G11C14/00 ,  G11C11/401 ,  H01L27/108 ,  H01L23/532

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

公开(公告)号：US10685708B2

公开(公告)日：2020-06-16

申请号：US16059317

申请日：2018-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Hoon Jeon ,  Yoo Cheol Shin ,  Jun Hee Lim ,  Sung Kweon Baek ,  Chan Ho Lee ,  Won Chul Jang ,  Sun Gyung Hwang

IPC: G11C14/00 ,  G11C11/401 ,  H01L27/108 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/105 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

公开(公告)号：US10103165B2

公开(公告)日：2018-10-16

申请号：US15481609

申请日：2017-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Hwan Son ,  Won Chul Jang ,  Dong Seog Eun ,  Jae Hoon Jang

IPC: H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.