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    Nonvolatile memory device and method of fabricating same
    1.
    发明授权
    Nonvolatile memory device and method of fabricating same 有权

    公开(公告)号：US11856772B2

    公开(公告)日：2023-12-26

    申请号：US16930381

    申请日：2020-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seung Won Lee ,  Tae Hun Kim ,  Min Cheol Park ,  Hye Ri Shin ,  Jun Hee Lim ,  Si Yeon Cho

    IPC: H01L27/115 ,  H10B43/27 ,  G11C8/14 ,  G11C7/18

    CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14

    Abstract: A nonvolatile memory device and method of fabricating same, the nonvolatile memory device including a substrate; a first semiconductor layer on the substrate; an etching stop film including a metal oxide on the first semiconductor layer; a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film; a channel hole penetrating through at least one of the mold structure, the etching stop film, the second semiconductor layer and the substrate; and a channel structure extending along a side wall of the channel hole, including an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film and a channel semiconductor sequentially formed along the side wall of the channel hole. The first semiconductor layer contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10319427B2

    公开(公告)日：2019-06-11

    申请号：US15794628

    申请日：2017-10-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chang Hoon Jeon ,  Yong Seok Kim ,  Jun Hee Lim

    IPC: G11C11/34 ,  G11C11/40

    Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

    Vertical-type memory device
    5.
    发明授权
    Vertical-type memory device 有权

    公开(公告)号：US11239249B2

    公开(公告)日：2022-02-01

    申请号：US16533193

    申请日：2019-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Jun Hee Lim ,  Kohji Kanamori

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L25/18 ,  H01L27/11573 ,  H01L21/02 ,  H01L21/311

    Abstract: A vertical-type memory device includes: a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate; first channel structures penetrating through the first gate structure and being in contact with the substrate; a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure; and second channel structures penetrating through the second gate structure and being in contact with the first channel structures. The first channel structures each may include a first channel layer penetrating the first gate structure, and a first channel pad disposed on the first channel layer and including a first pad region including n-type impurities and a second pad region including p-type impurities.

    Semiconductor Device
    7.
    发明申请
    Semiconductor Device 审中-公开

    公开(公告)号：US20180294264A1

    公开(公告)日：2018-10-11

    申请号：US15827231

    申请日：2017-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Uk Han ,  Taek Yong Kim ,  Satoru Yamada ,  Jun Hee Lim ,  Ki Jae Hur

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/762

    Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.

    Vertical memory device
    8.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US11024642B2

    公开(公告)日：2021-06-01

    申请号：US16508727

    申请日：2019-07-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Jun Hee Lim ,  Kohji Kanamori

    IPC: H01L27/11582

    Abstract: A vertical memory device includes a stacked structure including a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers extending in a direction perpendicular to an upper surface of the substrate on a first side surface of the stacked structure and spaced apart from each other in a direction parallel to the upper surface of the substrate, and a common source layer disposed between the stacked structure and the substrate and contacting the channel layers.

    Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate
    9.
    发明授权
    Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate 有权

    公开(公告)号：US10896711B2

    公开(公告)日：2021-01-19

    申请号：US16522121

    申请日：2019-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Hwan Lee ,  Seung Hyun Kim ,  Yong Seok Kim ,  Jun Hee Lim ,  Kohji Kanamori

    IPC: G11C11/22 ,  H01L27/11585

    Abstract: A memory device includes memory cells, the memory cells each including a first gate, a second gate electrically isolated from the first gate, a first gate insulating layer including a data storage layer having a ferroelectric material and disposed between the first gate and a channel region, a second gate insulating layer disposed between the second gate and the channel region, a first switching cell connected between the memory cells and a source line, and a second switching cell connected between the memory cells and a bit line. The second switching cell includes a third gate, a fourth gate, a third gate insulating layer not including a data storage layer having the ferroelectric material and the third gate disposed between the third gate and the channel region, and a fourth gate insulating layer disposed between the fourth gate and the channel region.

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