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公开(公告)号：US20190267088A1
公开(公告)日：2019-08-29
申请号：US16059317
申请日：2018-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang Hoon JEON , Yoo Cheol Shin , Jun Hee Lim , Sung Kweon Baek , Chan Ho Lee , Won Chul Jang , Sun Gyung Hwang
IPC: G11C14/00 , G11C11/401 , H01L27/108 , H01L23/532
Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.
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公开(公告)号：US20150132937A1
公开(公告)日：2015-05-14
申请号：US14444037
申请日：2014-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin Soak Kim , Gab Jin Nam , Dong Hwan Kim , Su Hwan Kim , Toshiro Nakanishi , Sung Kweon Baek , Tae Hyun An , Eun Ae Chung
IPC: H01L21/28
CPC classification number: H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/66795 , H01L29/7833
Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).
Abstract translation: 提供一种制造半导体器件的方法，包括：制备具有有源区的半导体衬底; 在所述有源区上形成用于栅极绝缘的介电层; 在介电层上形成含有锗（Ge）的材料的固化层; 热处理固化层; 并去除固化层。 含锗材料可以是硅锗（SiGe）或锗（Ge）。
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Patent Agency Ranking
公开(公告)号：US09443735B2
公开(公告)日：2016-09-13
申请号：US14444037
申请日：2014-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin Soak Kim , Gab Jin Nam , Dong Hwan Kim , Su Hwan Kim , Toshiro Nakanishi , Sung Kweon Baek , Tae Hyun An , Eun Ae Chung
IPC: H01L21/336 , H01L21/762 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/49
CPC classification number: H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/66795 , H01L29/7833
Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).
Abstract translation: 提供一种制造半导体器件的方法，包括：制备具有有源区的半导体衬底; 在所述有源区上形成用于栅极绝缘的介电层; 在介电层上形成含有锗（Ge）的材料的固化层; 热处理固化层; 并去除固化层。 含锗材料可以是硅锗（SiGe）或锗（Ge）。
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公开(公告)号：US20220059558A1
公开(公告)日：2022-02-24
申请号：US17210861
申请日：2021-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hak Seon Kim , Byung Joo Go , Sung Kweon Baek , Jae Hwa Seo , Chang Heon Lee
IPC: H01L27/11556 , H01L27/11582 , G11C5/06 , H01L29/06
Abstract: A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.
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公开(公告)号：US20240306384A1
公开(公告)日：2024-09-12
申请号：US18664547
申请日：2024-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hak Seon Kim , Byung Joo Go , Sung Kweon Baek , Jae Hwa Seo , Chang Heon Lee
CPC classification number: H10B41/27 , G11C5/06 , H01L29/0653 , H10B43/27
Abstract: A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.
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公开(公告)号：US12016177B2
公开(公告)日：2024-06-18
申请号：US17210861
申请日：2021-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hak Seon Kim , Byung Joo Go , Sung Kweon Baek , Jae Hwa Seo , Chang Heon Lee
CPC classification number: H10B41/27 , G11C5/06 , H01L29/0653 , H10B43/27
Abstract: A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.
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公开(公告)号：US10685708B2
公开(公告)日：2020-06-16
申请号：US16059317
申请日：2018-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang Hoon Jeon , Yoo Cheol Shin , Jun Hee Lim , Sung Kweon Baek , Chan Ho Lee , Won Chul Jang , Sun Gyung Hwang
IPC: G11C14/00 , G11C11/401 , H01L27/108 , H01L23/532 , H01L27/11582 , H01L27/105 , H01L27/11573
Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.
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