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公开(公告)号:US10685708B2
公开(公告)日:2020-06-16
申请号:US16059317
申请日:2018-08-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Hoon Jeon , Yoo Cheol Shin , Jun Hee Lim , Sung Kweon Baek , Chan Ho Lee , Won Chul Jang , Sun Gyung Hwang
IPC: G11C14/00 , G11C11/401 , H01L27/108 , H01L23/532 , H01L27/11582 , H01L27/105 , H01L27/11573
Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.
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公开(公告)号:US10685695B2
公开(公告)日:2020-06-16
申请号:US16405219
申请日:2019-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chang Hoon Jeon , Yong Seok Kim , Jun Hee Lim
IPC: G11C5/02 , G11C11/40 , G11C16/04 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/49 , H01L29/51
Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
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公开(公告)号:US10319427B2
公开(公告)日:2019-06-11
申请号:US15794628
申请日:2017-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chang Hoon Jeon , Yong Seok Kim , Jun Hee Lim
Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
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