公开(公告)号：US20240021575A1

公开(公告)日：2024-01-18

申请号：US18341381

申请日：2023-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Soo CHUNG ,  Won-Young KIM

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34

CPC classification number: H01L25/0652 ,  H01L23/5385 ,  H01L23/5383 ,  H01L23/481 ,  H01L25/0657 ,  H01L24/16 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/34 ,  H01L2224/16227 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H10B80/00

Abstract: A semiconductor package including a buffer structure including a first redistribution layer, a first buffer chip on the first redistribution layer, a second redistribution layer on the first buffer chip, and a first molding layer filling between the first redistribution layer and the second redistribution layer, and a first chip stack and a first semiconductor chip on the buffer structure and spaced apart from each other, wherein the first buffer chip overlaps at least a portion of the first semiconductor chip in a first direction from the buffer structure toward the first semiconductor chip, may be provided.

公开(公告)号：US20220199529A1

公开(公告)日：2022-06-23

申请号：US17392936

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Young KIM ,  Sunwon KANG

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Disclosed is a semiconductor package including a semiconductor chip that includes a chip pad on one surface of the semiconductor chip, a redistribution pattern on the one surface of the semiconductor chip and electrically connected to the chip pad, and a photosensitive dielectric layer between the semiconductor chip and the redistribution pattern. The photosensitive dielectric layer may be in physical contact with the redistribution pattern. The redistribution pattern includes a signal redistribution pattern, a ground redistribution pattern, and a power redistribution pattern. A vertical distance between the chip pad and the signal redistribution pattern may be greater than a width of the signal redistribution pattern.

公开(公告)号：US20240371808A1

公开(公告)日：2024-11-07

申请号：US18507617

申请日：2023-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Young KIM

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor structure may include an interposer die, a slave die, a plurality of first connection members and a plurality of second connection members. The interposer die may include a first surface and a second surface that is an opposite surface of the first surface. The slave die may include a third surface and a fourth surface that is an opposite surface of the third surface, and a plurality of through-silicon vias. The plurality of first connection members may be disposed on the first surface. The plurality of second connection members may electrically connect the second surface and the third surface.

公开(公告)号：US20240203939A1

公开(公告)日：2024-06-20

申请号：US18219394

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Dae-Woo KIM ,  Won-Young KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/80001

Abstract: A semiconductor package includes a power delivery network, a semiconductor chip on a top surface of the power delivery network, and having first and second surfaces opposite to each other, a second semiconductor chip on the top surface horizontally spaced from the first semiconductor chip, the second semiconductor chip having third surface and fourth surfaces, opposite to each other, chip stacks on the first semiconductor chip, and on the second semiconductor chip. The first surface is an active surface. The third surface is an active surface of the second semiconductor chip. The first chip stack includes third semiconductor chips on the first surface of the first semiconductor chip. The third semiconductor chips is disposed such that an active surface thereof faces the first semiconductor chip, and the first chip stack and the second semiconductor chip may be electrically connected to each other through the power delivery network.