公开(公告)号：US20230178468A1

公开(公告)日：2023-06-08

申请号：US17930942

申请日：2022-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonyoung KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/1434

Abstract: A memory module, includes a module substrate and at least one semiconductor package on the module substrate that includes a package substrate having a lower surface and an upper surface. First and second groups of lower pads are on the lower surface, and upper pads are on the upper surface and are electrically connected to the lower pads of the first group. A chip structure is on the upper surface of the package substrate and is electrically connected to the upper pads. First connection bumps connect the lower pads of the first group to the module substrate, and second connection bumps connect the lower pads of the second group to the module substrate. The first connection bumps have a first maximum width at a first distance from the package substrate, and the second connection bumps have a second maximum width at a second, shorter distance from the package substrate.

公开(公告)号：US20240297150A1

公开(公告)日：2024-09-05

申请号：US18500311

申请日：2023-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongpa HONG ,  Yeongkwon KO ,  Gunho CHANG ,  Wonkeun KIM ,  Wonyoung KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441

Abstract: A semiconductor package includes a base chip, a first semiconductor chip on the base chip, the first semiconductor chip including first through-vias, first bump structures on the first front surface of the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips including second through-vias, adhesive layers respectively on the second front surfaces of the plurality of second semiconductor chips, and an encapsulant between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips. The adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip.

公开(公告)号：US20220328373A1

公开(公告)日：2022-10-13

申请号：US17850221

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonyoung KIM

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor chip having chip pads on a first surface and having first and second side surfaces opposite to each other and third and fourth side surfaces opposite to each other, a molding member covering the third and fourth side surfaces and exposing the first and second side surfaces of the semiconductor chip, a redistribution wiring layer on a lower surface of the molding member to cover the first surface of the semiconductor chip and including a plurality of redistribution wirings electrically connected to the chip pads, and outer connection members arranged in a connection region defined on an outer surface of the redistribution wiring layer and electrically connected to the redistribution wirings.