公开(公告)号：US09293343B2

公开(公告)日：2016-03-22

申请号：US14705969

申请日：2015-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Haing Lee ,  Il-Sup Kim ,  Do-Hyoung Kim ,  Woo-Cheol Lee ,  Hyun-Ho Jung

IPC: H01L21/44 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/76816

Abstract: A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.

Abstract translation: 一种形成半导体器件的图案的方法包括：在基片上形成材料膜，在所述材料膜上形成硬掩模，在所述硬掩模上形成第一模具掩模图案和第二模具掩模图案，形成一对第一间隔物 以覆盖第一模具掩模图案的相对侧壁，以及一对第二间隔件，以覆盖第二模具掩模图案的相对的侧壁，形成第一间隙和第二间隙以通过去除第一模具掩模图案以暴露硬掩模，并且 第二模具掩模图案，所述第一间隙形成在所述一对第一间隔件和所述第二间隙之间，形成在所述一对第二间隔件之间，在所述硬掩模上形成掩模图案以覆盖所述第一间隙并暴露所述第二间隙， 辅助图案覆盖第二间隙，去除掩模图案; 以及通过使用第一间隔物，第二间隔物和辅助图案作为掩模来图案化硬掩模来形成硬掩模图案。

公开(公告)号：US10127051B2

公开(公告)日：2018-11-13

申请号：US14934419

申请日：2015-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Cheol Lee ,  Jin-Woo Roh ,  Moo-Young Kim ,  Dong-Wook Suh

IPC: G06F9/4401 ,  G06F1/32 ,  G06F9/50 ,  H04W52/02

Abstract: An electronic device includes a first processor; and a second processor; and a third processor. The second processor is configured to detect an event, select one of the first and third processors to perform one or more operations associated with the event, and cause the selected processor to perform the one or more operations.

公开(公告)号：US10116520B2

公开(公告)日：2018-10-30

申请号：US15068381

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Woo-Cheol Lee ,  Chang Lin Li ,  Tae Hee Han ,  Jinwoo Roh ,  Dongwook Suh

IPC: H04L12/26 ,  H04L12/24 ,  H04L12/773

Abstract: According to an exemplary embodiment of the present disclosure, a method of generating a network-on-chip (NoC) in an electronic device includes clustering a plurality of cores based on total communication energy comprising first communication energy between a plurality of voltage-frequency-islands (VFIs) and second communication energy inside the plurality of VFIs.

公开(公告)号：US20160269321A1

公开(公告)日：2016-09-15

申请号：US15068381

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Woo-Cheol Lee ,  Chang Lin Li ,  Tae Hee Han ,  Jinwoo Roh ,  Dongwook Suh

IPC: H04L12/933 ,  H04L12/733 ,  H04L12/24

CPC classification number: H04L41/145 ,  H04L45/60

Abstract: According to an exemplary embodiment of the present disclosure, a method of generating a network-on-chip (NoC) in an electronic device includes clustering a plurality of cores based on total communication energy comprising first communication energy between a plurality of voltage-frequency-islands (VFIs) and second communication energy inside the plurality of VFIs.

Abstract translation: 根据本公开的示例性实施例，在电子设备中生成片上网络（NoC）的方法包括：基于总通信能量聚集多个核心，所述总通信能量包括多个电压 - 频率 - 岛屿（VFI）和多个VFI内的第二通信能量。