公开(公告)号：US09997566B1

公开(公告)日：2018-06-12

申请号：US15602469

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Kuk Kim ,  Jong-Kyu Kim ,  Jong-Chul Park ,  Jong-Soon Park ,  Hye-Ji Yoon ,  Woo-Hyun Lee

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L29/423

CPC classification number: H01L27/228 ,  H01L27/222 ,  H01L29/4236 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.

公开(公告)号：US20180158867A1

公开(公告)日：2018-06-07

申请号：US15602469

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Kuk KIM ,  Jong-Kyu Kim ,  Jong-Chul Park ,  Jong-Soon Park ,  Hye-Ji Yoon ,  Woo-Hyun Lee

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  H01L27/222 ,  H01L29/4236 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.