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    Method of manufacturing a magnetoresistive random access memory device using hard masks and spacers
    1.
    发明授权
    Method of manufacturing a magnetoresistive random access memory device using hard masks and spacers 有权

    公开(公告)号：US10529919B2

    公开(公告)日：2020-01-07

    申请号：US16044666

    申请日：2018-07-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Han-Na Cho ,  Hye-Ji Yoon ,  O-Ik Kwon

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

    Abstract: A method of manufacturing an MRAM device including forming a first insulating interlayer and a lower electrode contact, the lower electrode contact extending through the first insulating interlayer; forming a lower electrode layer, a magnetic tunnel junction layer, an upper electrode layer, and a first hard mask layer on the first insulating interlayer and lower electrode contact; forming a second hard mask on the first hard mask layer; etching the first hard mask layer and upper electrode layer to form a first hard mask and upper electrode; forming a spacer on sidewalls of the upper electrode and hard masks; and etching the magnetic tunnel junction layer and the lower electrode layer to form a structure including a lower electrode and a magnetic tunnel junction pattern on the lower electrode contact, wherein a layer remains on the upper electrode after etching the magnetic tunnel junction layer and the lower electrode layer.

    Method of forming patterns and method of manufacturing a semiconductor device using the same
    4.
    发明授权
    Method of forming patterns and method of manufacturing a semiconductor device using the same 有权

    公开(公告)号：US09905754B1

    公开(公告)日：2018-02-27

    申请号：US15630046

    申请日：2017-06-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye-Ji Yoon ,  Yoo-Chul Kong ,  Jong-Kyu Kim ,  Sang-Kuk Kim ,  Yil-Hyung Lee

    IPC: H01L43/12 ,  H01L27/22

    CPC classification number: H01L43/12 ,  H01L27/222

    Abstract: In a method of forming a pattern of a semiconductor device, a first mask layer and an anti-reflective coating layer may be sequentially formed on a substrate. A photoresist layer may be formed on the anti-reflective coating layer. The photoresist layer may be exposed and developed to form a first preliminary photoresist pattern. A first ion beam etching process may be performed on the first preliminary photoresist pattern to form a second preliminary photoresist pattern. A second ion beam etching process may be performed on the second preliminary photoresist pattern to form a photoresist pattern. A second incident angle of an ion beam in the second ion beam etching process may be greater than a first incident angle of an ion beam in the first ion beam etching process. The anti-reflective coating layer and the first mask layer may be etched using the photoresist pattern as an etching mask to form a mask structure.

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