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公开(公告)号：US09953712B2
公开(公告)日：2018-04-24
申请号：US15680104
申请日：2017-08-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park , Seung-Bum Kim , Myung-Hoon Choi
CPC classification number: G11C16/14 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C16/3477
Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.
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公开(公告)号：US09852804B2
公开(公告)日：2017-12-26
申请号：US15281837
申请日：2016-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park , Hyun-Young Yoo , Sang-Soo Park
CPC classification number: G11C16/3431 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/021 , G11C29/028
Abstract: A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is performed on first memory cells connected to a first word line by using a first read voltage level. A read retry operation is, if the first read operation fails, performed on the first memory cells so that a read retry voltage level is set to a second read voltage level. A read offset table is determined based on a difference between the first read voltage level and the second read voltage level. The read offset table stores a plurality of read voltage offsets. A second read operation is performed on second memory cells connected to a second word line by using a third read voltage level determined using the read offset table.
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公开(公告)号：US12062660B2
公开(公告)日：2024-08-13
申请号：US17863042
申请日：2022-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： In-Keun Lee , Jong-Chul Park , Sang-Hyun Lee
IPC: H01L27/088 , H01L21/768 , H01L21/8234 , H01L29/66 , H01L29/78
CPC classification number: H01L27/0886 , H01L21/76832 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L29/66545 , H01L29/66795 , H01L29/7851
Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a first etch stop layer, a second etch stop layer, and an interlayer insulation layer that are stacked on the gate structure, and a contact plug penetrating the interlayer insulation layer, the second etch stop layer, and the first etch stop layer and contacting a sidewall of the gate structure. The contact plug includes a lower portion having a first width and an upper portion having a second width. A lower surface of the contact plug has a stepped shape.
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公开(公告)号：US10134980B2
公开(公告)日：2018-11-20
申请号：US15675089
申请日：2017-08-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park , Byoung-Jae Bae , Shin-Jae Kang , Young-Seok Choi
Abstract: In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.
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公开(公告)号：US20190333915A1
公开(公告)日：2019-10-31
申请号：US16360191
申请日：2019-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： In-Keun Lee , Jong-Chul Park , Sang-Hyun Lee
IPC: H01L27/088 , H01L29/66 , H01L29/78 , H01L21/768 , H01L21/8234
Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a first etch stop layer, a second etch stop layer, and an interlayer insulation layer that are stacked on the gate structure, and a contact plug penetrating the interlayer insulation layer, the second etch stop layer, and the first etch stop layer and contacting a sidewall of the gate structure. The contact plug includes a lower portion having a first width and an upper portion having a second width. A lower surface of the contact plug has a stepped shape.
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Patent Agency Ranking
公开(公告)号：US10454028B2
公开(公告)日：2019-10-22
申请号：US15630087
申请日：2017-06-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park
Abstract: A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.
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公开(公告)号：US11024397B2
公开(公告)日：2021-06-01
申请号：US16407761
申请日：2019-05-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul Bee Lee , Dong Hun Kwak , Jong-Chul Park
Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.
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公开(公告)号：US10825986B2
公开(公告)日：2020-11-03
申请号：US16658548
申请日：2019-10-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park
Abstract: A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.
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公开(公告)号：US09997566B1
公开(公告)日：2018-06-12
申请号：US15602469
申请日：2017-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Kuk Kim , Jong-Kyu Kim , Jong-Chul Park , Jong-Soon Park , Hye-Ji Yoon , Woo-Hyun Lee
IPC: H01L43/12 , H01L27/22 , H01L43/02 , H01L43/08 , H01L29/423
CPC classification number: H01L27/228 , H01L27/222 , H01L29/4236 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.
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公开(公告)号：US20180158867A1
公开(公告)日：2018-06-07
申请号：US15602469
申请日：2017-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Kuk KIM , Jong-Kyu Kim , Jong-Chul Park , Jong-Soon Park , Hye-Ji Yoon , Woo-Hyun Lee
CPC classification number: H01L27/228 , H01L27/222 , H01L29/4236 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.
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