公开(公告)号：US20220344361A1

公开(公告)日：2022-10-27

申请号：US17667156

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyong Jeon ,  Moorym Choi

IPC: H01L27/11526 ,  H01L27/11519 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

公开(公告)号：US11930638B2

公开(公告)日：2024-03-12

申请号：US17368029

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon ,  Junyoung Choi ,  Yoonjo Hwang

IPC: H10B43/27 ,  H10B12/00 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B12/50 ,  H10B43/40

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20230084497A1

公开(公告)日：2023-03-16

申请号：US17828170

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Moorym Choi ,  Junyoung Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A peripheral circuit structure may be formed on a first surface of a first substrate. A cell array structure may be formed on a first surface of a second substrate and may be attached to the peripheral circuit structure such that those first surfaces face each other. The cell array structure may be formed by forming a back-side via and a preliminary contact pad on the second substrate and forming a semiconductor layer. A hole may be formed to penetrate the semiconductor layer and to expose the preliminary contact pad and may be formed by removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer. The method may further include forming a stack on the semiconductor layer, an insulating layer on the stack, and a contact plug penetrating the insulating layer and connected to the contact pad.

公开(公告)号：US12262534B2

公开(公告)日：2025-03-25

申请号：US17667156

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyong Jeon ,  Moorym Choi

IPC: H10B41/40 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

公开(公告)号：US20230361033A1

公开(公告)日：2023-11-09

申请号：US18121456

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyong Jeon ,  Moorym Choi

IPC: H01L23/528 ,  H01L23/522 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A semiconductor device includes a substrate including a first region and a second region; insulating patterns in the substrate; gate electrodes provided below the substrate and spaced apart from each other in a first direction that is perpendicular to a lower surface of the substrate, the gate electrodes including pad regions arranged in a step shape below the second region; gate contact plugs passing through the pad regions of the gate electrodes, extending in the first direction, and vertically overlapping the insulating patterns; and a peripheral contact plug provided in an outer area of the substrate and extending from a level lower than a level of a lowermost gate electrode of the gate electrodes to a level higher than the lower surface of the substrate; and conductive patterns including a first conductive pattern provided on and connected to the peripheral contact plug, and second conductive patterns provided on and connected to the substrate.