公开(公告)号：US20230387056A1

公开(公告)日：2023-11-30

申请号：US18057305

申请日：2022-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunsun Jang ,  Jungtae Sung ,  Moorym Choi

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems. The three-dimensional semiconductor memory device includes a first substrate that includes a cell array region and a contact region, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure wherein the cell array structure includes interlayer dielectric layers and gate electrodes that are alternately stacked, a dielectric layer on the stack structure, and a second substrate on the stack structure, a mold structure that penetrates the stack structure and includes a dielectric material, and a first through structure and a second through structure that penetrate the mold structure and are spaced apart from each other.

公开(公告)号：US20240414912A1

公开(公告)日：2024-12-12

申请号：US18813670

申请日：2024-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjo Hwang ,  Jiyoung Kim ,  Jungtae Sung ,  Junyoung Choi

IPC: H10B41/27 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

公开(公告)号：US20220359442A1

公开(公告)日：2022-11-10

申请号：US17713478

申请日：2022-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/00

Abstract: A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.

公开(公告)号：US12096625B2

公开(公告)日：2024-09-17

申请号：US17375933

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjo Hwang ,  Jiyoung Kim ,  Jungtae Sung ,  Junyoung Choi

IPC: H10B41/27 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

公开(公告)号：US12051664B2

公开(公告)日：2024-07-30

申请号：US17543250

申请日：2021-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Jungtae Sung ,  Junyoung Choi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices on the first substrate, a lower interconnection structure on the circuit devices, and a lower bonding structure electrically connected to the lower interconnection structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, channel structures that penetrate the gate electrodes and extend in the first direction, and an upper bonding structure electrically connected to the gate electrodes and the channel structures and bonded to the lower bonding structure. The second semiconductor structure further includes a first via connected to an upper portion of the second substrate, a second via spaced apart from the first via and the second substrate, and a contact plug.

公开(公告)号：US20230140000A1

公开(公告)日：2023-05-04

申请号：US17834977

申请日：2022-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung ,  Yunsun Jang

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/417

Abstract: A semiconductor device includes first and second substrates including cell and peripheral circuit regions, first and second gate electrode structures, first and second channels, and first to third transistors. The first and second gate electrode structures include first and second gate electrodes in a vertical direction. The first and second channel extend through the first and second gate electrode structures. The first transistor is on the peripheral circuit region. The second gate electrode structure is on the first gate electrode structure and the first transistor. The second and third transistors are on the second gate electrode structure. The second substrate is on the second and third transistors. The first and second channels do not directly contact each other, are electrically connected with each other, and receive electrical signals from the second transistor. The first and third transistors apply electrical signals to the first and second gate electrode structures.

公开(公告)号：US11930638B2

公开(公告)日：2024-03-12

申请号：US17368029

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon ,  Junyoung Choi ,  Yoonjo Hwang

IPC: H10B43/27 ,  H10B12/00 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B12/50 ,  H10B43/40

Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

公开(公告)号：US20230084497A1

公开(公告)日：2023-03-16

申请号：US17828170

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Moorym Choi ,  Junyoung Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A peripheral circuit structure may be formed on a first surface of a first substrate. A cell array structure may be formed on a first surface of a second substrate and may be attached to the peripheral circuit structure such that those first surfaces face each other. The cell array structure may be formed by forming a back-side via and a preliminary contact pad on the second substrate and forming a semiconductor layer. A hole may be formed to penetrate the semiconductor layer and to expose the preliminary contact pad and may be formed by removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer. The method may further include forming a stack on the semiconductor layer, an insulating layer on the stack, and a contact plug penetrating the insulating layer and connected to the contact pad.

公开(公告)号：US11600609B2

公开(公告)日：2023-03-07

申请号：US17204394

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungtae Sung ,  Junyoung Choi ,  Jiyoung Kim ,  Yoonjo Hwang

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems including the same. The three-dimensional semiconductor memory device comprises a first structure and a second structure in contact with the first structure. Each of the first and second structures includes a substrate, a peripheral circuit region on the substrate, and a cell array region including a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures. The stack structure is between the peripheral circuit region and the common source region. The common source regions of the first and second structures are connected with each other.

公开(公告)号：US20220139944A1

公开(公告)日：2022-05-05

申请号：US17375933

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjo Hwang ,  Jiyoung Kim ,  Jungtae Sung ,  Junyoung Choi

IPC: H01L27/11556 ,  G11C5/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582

Abstract: A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.