公开(公告)号：US20240370335A1

公开(公告)日：2024-11-07

申请号：US18778475

申请日：2024-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  KIJUN LEE ,  MYUNGKYU LEE ,  YEONGGEOL SONG ,  Jinhoon Jang ,  SUNGHYE CHO ,  Isak Hwang

IPC: G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US20240248850A1

公开(公告)日：2024-07-25

申请号：US18416558

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEHYUN KIM ,  SEONGMUK KANG ,  JIHO KIM ,  KYOMIN SOHN ,  YEONGGEOL SONG ,  KIJUN LEE ,  MYUNGKYU LEE ,  SUKHAN LEE

IPC: G06F12/0891 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F12/126

Abstract: A memory system includes a system controller and a memory device. The system controller includes a memory controller configured to transmit a received address to a decoding module, and output, to the host device, decoded data. The decoding module includes a cache device and a decoder. The decoding module is configured to receive the data corresponding to the address from the memory device. The decoding module is configured transmit the data stored in the cache device to the memory controller in response to determining that the data corresponding to the address is stored in the cache device. The decoding module is configured to decode the data corresponding to the address to generate decoded data and store the decoded result in the cache device in response to determining that the data corresponding to the address is not stored in the cache device.

公开(公告)号：US20210334033A1

公开(公告)日：2021-10-28

申请号：US17090726

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHYE CHO ,  KIJUN LEE ,  SUNG-RAE KIM ,  CHANKI KIM ,  YEONGGEOL SONG ,  YESIN RYU ,  JAEYOUN YOUN ,  MYUNGKYU LEE

IPC: G06F3/06

Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

公开(公告)号：US20210224156A1

公开(公告)日：2021-07-22

申请号：US16926000

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHYE CHO ,  KIJUN LEE ,  YEONGGEOL SONG ,  SUNGRAE KIM ,  CHANKI KIM ,  MYUNGKYU LEE ,  SANGUHN CHA

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00

Abstract: An error correction circuit of a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.