公开(公告)号：US12176919B2

公开(公告)日：2024-12-24

申请号：US17988140

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Jin-Hoon Jang ,  Isak Hwang

IPC: H03M13/00 ,  G11C29/00 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15

Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

公开(公告)号：US20240370335A1

公开(公告)日：2024-11-07

申请号：US18778475

申请日：2024-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  KIJUN LEE ,  MYUNGKYU LEE ,  YEONGGEOL SONG ,  Jinhoon Jang ,  SUNGHYE CHO ,  Isak Hwang

IPC: G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US20230367672A1

公开(公告)日：2023-11-16

申请号：US18226622

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10

CPC classification number: G06F11/1068

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US12066893B2

公开(公告)日：2024-08-20

申请号：US18226622

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F11/1068

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US11762736B2

公开(公告)日：2023-09-19

申请号：US17580048

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/28 ,  G06F13/16 ,  G06F11/30

CPC classification number: G06F11/1068

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US20220374309A1

公开(公告)日：2022-11-24

申请号：US17580048

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.