公开(公告)号：US20200243123A1

公开(公告)日：2020-07-30

申请号：US16848364

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on;enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20210405683A1

公开(公告)日：2021-12-30

申请号：US17145211

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung PARK ,  YOUNG-HOON SON ,  HYUN-YOON CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

IPC: G06F1/06 ,  G06F13/40 ,  G11C11/403 ,  G11C11/406

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

公开(公告)号：US20210233575A1

公开(公告)日：2021-07-29

申请号：US17141357

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20180342274A1

公开(公告)日：2018-11-29

申请号：US15918526

申请日：2018-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  G11C7/10 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20230280782A1

公开(公告)日：2023-09-07

申请号：US18196242

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung PARK ,  YOUNG-HOON SON ,  HYUN-YOON CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

IPC: G06F1/06 ,  G11C11/406 ,  G11C11/403 ,  G06F13/40

CPC classification number: G06F1/06 ,  G11C11/40607 ,  G11C11/403 ,  G06F13/4022

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

公开(公告)号：US20200135247A1

公开(公告)日：2020-04-30

申请号：US16721131

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  G11C7/10 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20180374823A1

公开(公告)日：2018-12-27

申请号：US15995181

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  JUNG-HWAN CHOI ,  SEOK-HUN HYUN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498

Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.