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    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230223060A1

    公开(公告)日：2023-07-13

    申请号：US17939016

    申请日：2022-09-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： BAEK JIN LIM ,  YOUNGCHUL CHO ,  SEUNGJIN PARK ,  DOOBOCK LEE ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

    IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

    Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

    SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND TEST SYSTEM
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND TEST SYSTEM 有权

    公开(公告)号：US20220076778A1

    公开(公告)日：2022-03-10

    申请号：US17239651

    申请日：2021-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANGLOK KIM ,  YOUNGDON CHOI

    IPC: G11C29/56

    Abstract: A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.

    INJECTION LOCKING OSCILLATOR CIRCUIT AND OPERATING METHOD
    7.
    发明申请
    INJECTION LOCKING OSCILLATOR CIRCUIT AND OPERATING METHOD 有权

    公开(公告)号：US20220069812A1

    公开(公告)日：2022-03-03

    申请号：US17224577

    申请日：2021-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG CHOI ,  WONJOO JUNG ,  YOUNGCHUL CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

    IPC: H03K5/01

    Abstract: An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

    CLOCK CONVERTING CIRCUIT WITH SYMMETRIC STRUCTURE
    8.
    发明申请
    CLOCK CONVERTING CIRCUIT WITH SYMMETRIC STRUCTURE 有权

    公开(公告)号：US20210405683A1

    公开(公告)日：2021-12-30

    申请号：US17145211

    申请日：2021-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung PARK ,  YOUNG-HOON SON ,  HYUN-YOON CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

    IPC: G06F1/06 ,  G06F13/40 ,  G11C11/403 ,  G11C11/406

    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

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