公开(公告)号：US20230016628A1

公开(公告)日：2023-01-19

申请号：US17566832

申请日：2021-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGGUL SONG ,  JUNYEONG SEOK ,  EUN CHU OH ,  BYUNGCHUL JANG ,  JOONSUNG LIM

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/532

Abstract: Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.

公开(公告)号：US20230154537A1

公开(公告)日：2023-05-18

申请号：US17935122

申请日：2022-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGGUL SONG ,  Junyeong Seok ,  Eun Chu Oh ,  Byungchul Jang

IPC: G11C16/04 ,  G11C16/08 ,  H01L27/115 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H01L27/115

Abstract: A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

公开(公告)号：US20230015496A1

公开(公告)日：2023-01-19

申请号：US17577771

申请日：2022-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUN CHU OH ,  BYUNGCHUL JANG ,  JUNYEONG SEOK ,  YOUNGGUL SONG ,  JOONSUNG LIM

IPC: G06F3/06

Abstract: A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.