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    STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES
    1.
    发明申请
    STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES 有权

    公开(公告)号：US20230054754A1

    公开(公告)日：2023-02-23

    申请号：US17702291

    申请日：2022-03-23

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

    IPC分类号： G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074

    摘要： A storage device includes a NAND flash memory device, an auxiliary memory device and a storage controller to control the NAND flash memory device and the auxiliary memory device. The storage controller includes a processor, an error correction code (ECC) engine and a memory interface. The processor executes a flash translation layer (FTL) loaded onto an on-chip memory. The ECC engine generates first parity bits for user data to be stored in a target page of the NAND flash memory device based on error attribute of a target memory region associated with the target page, and selectively generates additional parity bits for the user data under control of the processor. The memory interface transmits the user data and the first parity bits to the NAND flash memory device, and selectively transmits the additional parity bits to the auxiliary memory device.

    STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES
    3.
    发明申请
    STORAGE DEVICES AND METHODS OF OPERATING STORAGE DEVICES 有权

    公开(公告)号：US20230112694A1

    公开(公告)日：2023-04-13

    申请号：US17750581

    申请日：2022-05-23

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Wijik Lee ,  Byungchul Jang

    IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C7/10

    摘要： A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

    Memory system for performing recovery operation, memory device, and method of operating the same
    8.
    发明授权
    Memory system for performing recovery operation, memory device, and method of operating the same 有权

    公开(公告)号：US11989091B2

    公开(公告)日：2024-05-21

    申请号：US17965091

    申请日：2022-10-13

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Younggul Song ,  Byungchul Jang ,  Junyeong Seok ,  Eun Chu Oh

    IPC分类号： G06F11/10 ,  G06F11/07

    CPC分类号： G06F11/1068 ,  G06F11/076 ,  G06F11/0793

    摘要： A method of operating a memory system that comprises a memory device including a plurality of memory blocks and a memory controller, includes detecting a first memory block having a degradation count greater than or equal to a first reference value by the memory controller. A first command for the first memory block is transmitted to the memory device by the memory controller. A first voltage is applied to all of a plurality of word lines connected to the first memory block and a second voltage to a bit line connected to the first memory block in response to the first command by the memory device. The first voltage is greater than a voltage applied to turn on memory cells connected to all of the plurality of word lines. The second voltage is greater than a voltage applied to the bit line during program, read or erase operations.