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    RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY SYSTEM
    1.
    发明申请
    RESISTIVE MEMORY SYSTEM AND METHOD OF OPERATING THE RESISTIVE MEMORY SYSTEM 有权
    电阻记忆系统和操作电阻记忆系统的方法

    公开(公告)号：US20160240252A1

    公开(公告)日：2016-08-18

    申请号：US15042516

    申请日：2016-02-12

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： EUN CHU OH ,  JUN JIN KONG ,  YOUNG BAE KIM ,  HONG RAK SON ,  PIL SANG YOON ,  HAN SHIN SHIN

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0076

    摘要： A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

    摘要翻译： 具有多个存储单元的电阻式存储器系统包括具有电阻性存储单元阵列和控制器的存储器件。 控制器通过对输入数据进行编码来产生要写入存储单元阵列的写入数据，使得输入数据对应于存储单元可能具有的擦除状态和多个编程状态。 编码输入数据使得分配了第一编程状态的存储器单元的数量和分配有第二编程状态的存储单元的数量中的至少一个小于擦除状态下的至少一个存储单元，并且 其他编程状态。 第一编程状态在多个编程状态中具有最高的电阻电平，并且第二编程状态在多个编程状态中具有第二高的电阻电平。

    NONVOLATLE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME, AND RELATED MEMORY MANAGEMENT, ERASE AND PROGRAMMING METHODS
    2.
    发明申请
    NONVOLATLE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME, AND RELATED MEMORY MANAGEMENT, ERASE AND PROGRAMMING METHODS 审中-公开
    不具有存储器的存储器件和存储器系统以及相关的存储器管理，擦除和编程方法

    公开(公告)号：US20160293263A1

    公开(公告)日：2016-10-06

    申请号：US15178135

    申请日：2016-06-09

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： EUN CHU OH ,  JONGHA KIM ,  JUNJIN KONG

    IPC分类号： G11C16/16 ,  G06F12/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    CPC分类号： G11C16/16 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/3445

    摘要： An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.

    摘要翻译： 非易失性存储器件的擦除方法包括设置擦除模式，以及根据所设置的擦除模式执行正常擦除操作和快速擦除操作之一。 执行正常擦除操作以将存储器单元的阈值电压设置为低于第一擦除验证电平的擦除状态。 执行快速擦除操作以将存储器单元的阈值电压设置为低于第二擦除验证电平的伪擦除状态。 第二擦除验证级别高于第一擦除验证级别。

    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230016628A1

    公开(公告)日：2023-01-19

    申请号：US17566832

    申请日：2021-12-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： YOUNGGUL SONG ,  JUNYEONG SEOK ,  EUN CHU OH ,  BYUNGCHUL JANG ,  JOONSUNG LIM

    IPC分类号： H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/532

    摘要： Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.

    NONVOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE SAME
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230015496A1

    公开(公告)日：2023-01-19

    申请号：US17577771

    申请日：2022-01-18

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： EUN CHU OH ,  BYUNGCHUL JANG ,  JUNYEONG SEOK ,  YOUNGGUL SONG ,  JOONSUNG LIM

    IPC分类号： G06F3/06

    摘要： A nonvolatile memory (NVM) device includes a plurality of memory blocks and a control logic receiving a specific command and an address. The control logic may perform a cell count-based dynamic read (CDR) operation on memory cells connected to one of wordlines of a selected block, among the plurality of memory blocks, in response to the address. The control logic includes a cell count comparator circuit configured to compare: (1) a first cell count value for a highest state among a plurality of states with at least one reference value according to the CDR operation and (2) a second cell count value for an erase state among the plurality of states with the at least one reference value. Additionally, the control logic includes a read level selector configured to select a read level according to a result of the comparison of the cell count comparator circuit.