公开(公告)号：US10580688B2

公开(公告)日：2020-03-03

申请号：US16037460

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul Yoon ,  Yeong-Shin Park ,  Joonghee Kim ,  Jihee Kim ,  Dongjun Shin ,  Kukhan Yoon ,  Taeseop Choi ,  Jungheun Hwang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12

Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.

公开(公告)号：US10410919B2

公开(公告)日：2019-09-10

申请号：US15296202

申请日：2016-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Shin Park ,  Young-Jae Kim

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop layer covering the lower insulating layer and the lower wiring, forming an interlayer insulating layer on the etch stop layer, forming a preliminary via-hole through the interlayer insulating layer, partially etching the interlayer insulating layer to form a trench partially merged with the preliminary via-hole and a via-hole defined by a remaining portion of the preliminary via-hole, removing the etch stop layer exposed by the via-hole to expose the lower wiring, partially etching a contact area at which the trench and the via-hole are in contact with each other and forming an upper wiring in the via-hole and the trench to be electrically connected to the lower wiring.

公开(公告)号：US20190214295A1

公开(公告)日：2019-07-11

申请号：US16037460

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul YOON ,  Yeong-Shin Park ,  Joonghee Kim ,  Jihee Kim ,  Dongjun Shin ,  Kukhan Yoon ,  Taeseop Choi ,  Jungheun Hwang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.