公开(公告)号：US20180174959A1

公开(公告)日：2018-06-21

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju KIM ,  Su-A KIM ,  Soo-Young KIM ,  Min-Woo WON ,  Bok-Yeon WON ,  Ji-Suk KWON ,  Young-Ho KIM ,  Ji-Hak YU ,  Hyun-Chul YOON ,  Seok-Jae LEE ,  Sang-Keun HAN ,  Woong-Dai KANG ,  Hyuk-Joon KWON ,  Bum-Jae LEE

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/552 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5225 ,  G11C7/06 ,  G11C7/1057 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/06 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/06159 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/3025

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US20240428847A1

公开(公告)日：2024-12-26

申请号：US18661809

申请日：2024-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul YOON ,  Youngcheol CHAE

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094

Abstract: A memory device including: a memory cell array including a first memory cell connected to a bit line, and a second memory cell connected to a complementary bit line; a bit line sense amplifier including a sensing bit line and a sensing complementary bit line; a first charge transfer transistor between the bit line and the sensing bit line; a second charge transfer transistor between the complementary bit line and the sensing complementary bit line; a first pre-charge transistor pre-charging the bit line and the complementary bit line with a first pre-charge voltage; a second pre-charge transistor pre-charging the sensing bit line and the sensing complementary bit line with a second pre-charge voltage; a first transfer gate transistor providing a first transfer gate voltage to the first charge transfer transistor; and a second transfer gate transistor providing a second transfer gate voltage to the second charge transfer transistor.

公开(公告)号：US20190214295A1

公开(公告)日：2019-07-11

申请号：US16037460

申请日：2018-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul YOON ,  Yeong-Shin Park ,  Joonghee Kim ,  Jihee Kim ,  Dongjun Shin ,  Kukhan Yoon ,  Taeseop Choi ,  Jungheun Hwang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Disclosed is a method of fabricating a semiconductor device. The method comprises stacking an etching target layer, a first mask layer, an under layer, and a photoresist layer on a substrate, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, and performing a nitrogen plasma treatment on the photoresist pattern while using the first mask layer as an etching stop layer, the performing continuing until a top surface of the first mask layer is exposed. During the performing, the under layer is etched to form an under pattern below the photoresist pattern.

公开(公告)号：US20190096508A1

公开(公告)日：2019-03-28

申请号：US16023584

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Ryun KIM ,  Hyun-Chul YOON

IPC: G11C29/00 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.