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    Semiconductor memory device and sense amplifier control method thereof
    4.
    发明授权
    Semiconductor memory device and sense amplifier control method thereof 有权
    半导体存储器件及其读出放大器的控制方法

    公开(公告)号：US09269420B2

    公开(公告)日：2016-02-23

    申请号：US14253353

    申请日：2014-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kichul Chun ,  Hyun-Chul Yoon

    IPC: G11C11/24 ,  G11C11/4094 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4074

    CPC classification number: G11C11/4094 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4091

    Abstract: A semiconductor memory device is provided. A cell array includes a DRAM cell connected to one of a pair of bit lines. A bit line sense amplifier is coupled to the pair of bit lines. The bit line sense amplifier discharges a low-level bit line of the pair of bit lines toward a ground level and clamps the low-level bit line to a boosted sense ground voltage in response to a control signal. A sense amplifier control logic generates the control signal having a pulse interval. The low-level bit line is discharged toward the ground level for the pulse interval and after the pulse interval ends, the low-level bit line is clamped to the boosted sense ground voltage.

    Abstract translation: 提供半导体存储器件。 单元阵列包括连接到一对位线之一的DRAM单元。 位线读出放大器耦合到一对位线。 位线读出放大器将一对位线的低电平位线朝向接地电平放电，并且响应于控制信号将低电平位线钳位到升压检测接地电压。 读出放大器控制逻辑产生具有脉冲间隔的控制信号。 低电平位线在脉冲间隔内向地电平放电，脉冲间隔结束后，低电平位线被钳位到升压检测接地电压。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230094529A1

    公开(公告)日：2023-03-30

    申请号：US17807146

    申请日：2022-06-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JINYOUNG PARK ,  Sangwuk Park ,  Hyun-Chul Yoon ,  Jungpyo Hong

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes active sections that include first and second impurity regions and are defined by a device isolation layer. Word lines extend in a first direction on the active sections. Intermediate dielectric patterns cover top surfaces of the word lines. Bit-line structures extend on the word lines in a second direction intersecting the first direction. Contact plugs are disposed between the bit-line structures and are connected to the second impurity regions. Data storage elements are disposed on the contact plugs. The intermediate dielectric pattern includes a capping part that covers the top surfaces of the word lines and is buried in the substrate. Fence parts extend between the bit-line structures from the capping part.

    MEMORY DEVICE
    7.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20250056795A1

    公开(公告)日：2025-02-13

    申请号：US18441968

    申请日：2024-02-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyoung Lee ,  Hyun-Chul Yoon ,  Yeongwoo Kang

    IPC: H10B20/00 ,  G11C29/04 ,  H10B12/00 ,  H10B20/25

    Abstract: The present disclosure relates to memory devices. An example memory device includes a memory cell region including a memory cell array is configured to store data, and an antifuse cell array including a plurality of antifuse bit lines, a plurality of antifuse word lines, and a plurality of program transistors that is electrically coupled to a first antifuse bit line among the plurality of antifuse bit lines and that are coupled in parallel with one another. The memory device includes a peripheral circuit region including an antifuse sense amplifier is configured to output one-time programmable (OTP) data stored in the plurality of program transistors.

    Method of fabricating semiconductor device using multipe photolithography for patterning
    9.
    发明授权
    Method of fabricating semiconductor device using multipe photolithography for patterning 有权

    公开(公告)号：US11610898B2

    公开(公告)日：2023-03-21

    申请号：US17237208

    申请日：2021-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Chul Yoon ,  Sungun Kwon ,  Hanseung Kwak ,  Jihee Kim ,  Sunghoon Choi

    IPC: H01L27/108

    Abstract: Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.

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