公开(公告)号：US20230066367A1

公开(公告)日：2023-03-02

申请号：US17693328

申请日：2022-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung PARK ,  Hyuk KIM ,  Yeongeun YOOK

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower structure including lower wirings. A horizontal wiring layer is disposed on the lower structure while including a horizontal conductive layer, and a horizontal insulating layer extending through the horizontal conductive layer. A stack structure is disposed on the horizontal wiring layer. A channel structure extending into the horizontal wiring layer while extending through the stack structure is provided. A through electrode connected to the lower wirings while extending through the stack structure and the horizontal insulating layer is provided. The stack structure includes insulating layers and electrode layers repeatedly alternately stacked, and an interlayer insulating layer disposed at side surfaces of the insulating layers and the electrode layers. The through electrode includes a first portion extending into the interlayer insulating layer, and a second portion disposed between the first portion and the lower wirings while having a smaller horizontal width than the first portion.

公开(公告)号：US20230209826A1

公开(公告)日：2023-06-29

申请号：US18080325

申请日：2022-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongeun YOOK ,  Hyuk KIM ,  Youngsik LEE

IPC: H10B43/27 ,  H01L23/535 ,  H10B43/40

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first region and a second region, the second region extending from the first region; a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, the stack having a staircase structure on the second region; an insulating layer covering the staircase structure of the stack; first vertical channel structures on the first region, penetrating the stack, and in contact with the substrate; first contact plugs on the second region and penetrating the insulating layer and the stack; and first insulating pads in the insulating layer and enclosing upper portions of the first contact plugs, respectively, wherein the first insulating pads overlap with the first vertical channel structures in a horizontal direction.

公开(公告)号：US20240429052A1

公开(公告)日：2024-12-26

申请号：US18660507

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Bongcheol KIM ,  Sangho LEE ,  Yeongeun YOOK

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/311

Abstract: A method of manufacturing a semiconductor device includes sequentially forming an etch target film and an insulating film on a substrate. A first photoresist film is formed on the insulating film. A first photoresist pattern is formed exposing a first region of the insulating film by patterning the first photoresist film. A protective film is formed covering the first photoresist pattern and the first region of the insulating film. A second photoresist pattern is formed exposing a second region of the protective film. The protective film covers the first photoresist pattern during the forming of the second photoresist pattern. A first trench is formed by etching the etch target film using the first photoresist pattern. A second trench is formed by etching the etch target film using the second photoresist pattern. The forming of the first trench is performed after the forming of the second photoresist pattern.