公开(公告)号：US20240407150A1

公开(公告)日：2024-12-05

申请号：US18737605

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC: H10B12/00

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US11380552B2

公开(公告)日：2022-07-05

申请号：US16858591

申请日：2020-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Yoon ,  Mincheol Kwak ,  Joonghee Kim ,  Jihee Kim ,  Yeongshin Park ,  Jungheun Hwang

IPC: H01L21/308 ,  H01L27/108

Abstract: In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.

公开(公告)号：US20210210493A1

公开(公告)日：2021-07-08

申请号：US17028763

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H01L27/108

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US12022645B2

公开(公告)日：2024-06-25

申请号：US17398136

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/50

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US12238920B2

公开(公告)日：2025-02-25

申请号：US17971256

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H10B12/00 ,  H01L21/764 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US20230037972A1

公开(公告)日：2023-02-09

申请号：US17971256

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/66 ,  H01L21/764

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.

公开(公告)号：US11508732B2

公开(公告)日：2022-11-22

申请号：US17028763

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihee Kim ,  Yeongshin Park ,  Hyunchul Yoon ,  Joonghee Kim ,  Jungheun Hwang

IPC: H01L27/108 ,  H01L21/768 ,  H01L29/66 ,  H01L21/764

Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.